DS581 Datasheet, PDF (11/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
Table 1: XPS EPC IP Core Design Parameters (Contd)
Generic Feature/Description
Parameter Name
Allowable Values
Default
Value
VHDL
Type
Notes:
1. The generic C_PRH_CLK_SUPPORT is relevant only when the device is configured for synchronous access i.e.
C_PRHx_SYNC = 1. If more than one device is synchronous, then the frequency for the peripheral clock (PRH_Clk)
should be chosen as the minimum of the operating frequencies of those devices. In a system that includes
asynchronous as well as synchronous mode in the same instance of the XPS EPC core, the external clock support is
not allowed.
2. The C_PRH_MAX_ADWIDTH determines the size of the data bus. For all non multiplexed devices the
C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all external devices i.e. C_PRH_MAX_ADWIDTH
equals C_PRH_MAX_DWIDTH. However, if any of the devices is configured for multiplexed address and data bus,
then C_PRH_MAX_ADWIDTH should be set as the maximum of data bus of all external devices and the address bus
of device(s) employing multiplexed address and data bus.
3. Current version of the XPS EPC do not support the burst transactions to/from the PLB.
4. ’x’ in the generic refers to the number of the peripheral device and takes a value in the range of 0 to
C_NUM_PERIPHERALS - 1.
5. XPS EPC design can accommodate up to four peripheral devices. The address range for the devices are designated
as C_PRHx_BASEADDR, C_PRHx_HIGHADDR etc.
6. The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR must comprise a contiguous range and the
size of the range must be a power of two i.e. size of range = 2^m. Further, the ’m’ least significant bits of
C_PRHx_BASEADDR must be zero. The base and high address range assigned to different peripherals must be
mutually exclusive.
7. No default value will be specified to ensure that the actual value is set i.e. if the value is not set, a compiler error will
be generated.
8. C_PRHx_FIFO_ACCESS must be set to 1 if the support for access to FIFO within external peripheral device is to be
included.
9. C_PRHx_FIFO_OFFSET is the byte offset of the external peripheral FIFO from the base address
(C_PRHx_BASEADDR) of the peripheral irrespective of the data width of the peripheral device. If
C_PRHx_FIFO_ACCESS = 1, then C_PRHx_FIFO_OFFSET must be set to a valid offset within the address range
assigned to the peripheral.
10. The generic C_PRHx_DWIDTH_MATCH is relevant only when the width of the peripheral data (PRH_Data) bus is
less than the PLB data bus (PLB_wrDBus). The generic C_PRHx_DWIDTH_MATCH must be set to ’1’ in such cases.
11. Address setup time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are
multiplexed i.e. C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode.
Address setup time is with respect to falling edge of read/write signals (PRH_Wr_n/PRH_Rd_n), if the device is non
multiplexed and is relevant only if the access mode is asynchronous.
12. Value for the parameter must be assigned if the address and the data bus are multiplexed i.e.
C_PRHx_BUS_MULTIPLEX = 1. This parameter assignment is applicable for synchronous and asynchronous
devices.
13. Address hold time is with respect to falling edge of address strobe (PRH_ADS) if the address and the data bus are
multiplexed i.e. C_PRHx_BUS_MULTIPLEX = 1 and must be set both in synchronous and asynchronous mode.
Address hold time is with respect to rising edge of read/write signals (PRH_Wr_n/PRH_Rd_n) if the address and the
data bus are separate and is relevant only if the access mode is asynchronous.
14. Value must be assigned if the access mode of the peripherals is asynchronous i.e. C_PRHx_SYNC = 0. If the access
mode of the peripheral is synchronous i.e. C_PRHx_SYNC = 1, then the zero should be assigned to the parameter.
15. Write signal (PRH_Wr_n) low time is the maximum of C_PRHx_WRN_WIDTH and C_PRHx_DATA_TSU.
16. The value of C_PRHx_WRN_WIDTH must be smaller than C_PRHx_WR_CYCLE. The C_PRHx_WR_CYCLE time
will be considered for the buffer period between consecutive writes.
17. In non-multiplexed address and data bus mode, write recovery time will be maximum of C_PRHx_ADDR_TH,
C_PRHx_CSN_TH, C_PRHx_DATA_TH and PRH_Wr_n high time (i.e. C_PRHx_WR_CYCLE minus
C_PRHx_WRN_WIDTH). If the peripheral uses multiplexed address and data bus, then the write recovery time will be
maximum of C_PRHx_CSN_TH, C_PRHx_DATA_TH and PRH_Wr_n high time.
18. Read signal (PRH_Rd_n) low time is the maximum of C_PRHx_RDN_WIDTH and C_PRHx_DATA_TOUT.
19. The value of C_PRHx_RDN_WIDTH must be smaller than C_PRHx_RD_CYCLE.The C_PRHx_RD_CYCLE time will
be considered for the buffer period between consecutive reads.
20. In non-multiplexed address and data bus mode, read recovery time will be maximum of C_PRHx_ADDR_TH,
C_PRHx_CSN_TH, C_PRHx_DATA_TINV and PRH_Rd_n high time (i.e. C_PRHx_RD_CYCLE minus
C_PRHx_RDN_WIDTH). If the peripheral uses multiplexed address and data bus, then the read recovery time will be
maximum of C_PRHx_CSN_TH, C_PRHx_DATA_TINV and PRH_Rd_n high time.
21. Device ready validity period (C_PRHx_RDY_TOUT) must be set as the maximum of the device ready values specified
for read and write transactions for that device.
22. Device ready pulse width (C_PRHx_RDY_WIDTH) must be set as the maximum of the device ready values specified
for read and write transactions for that device.
23. Device ready validity (C_PRHx_RDY_TOUT) period must be less than device ready signal width
(C_PRHx_RDY_WIDTH). Device ready signal width (C_PRHx_RDY_WIDTH) must be set for both synchronous and
asynchronous access mode in order to prevent the device from holding the PLB indefinitely.
DS581 September 16, 2009
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Product Specification