DS581 Datasheet, PDF (47/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
System Performance
To measure the system performance (Fmax) of this core, this core was added to a Virtex-4 system, a
Virtex-5 system, and a Spartan-3A system as the Device Under Test (DUT) as shown in Figure 26,
Figure 27, and Figure 28.
Because the XPS EPC IP core will be used with other design modules in the FPGA, the utilization and
timing numbers reported in this section are estimates only. When this core is combined with other
designs in the system, the utilization of FPGA resources and timing of the core design will vary from
the results reported here.
Figure Top x-ref 26
PLBV46
PLBV46
MPMC
XPS CDMA XPS CDMA
Device Under
Test (DUT)
IPLB1 DPLB1
DPLB0
PowerPC 405
Processor ^IPLB0
PLBV46
Figure Top x-ref 27
XPS BRAM XPS INTC XPS GPIO
Figure 26: Virtex-4 FX System
XPS UART
Lite
DS581_26_080309
MMPicircroorcoBeBl_sa^l_sazozeer
PLBV46
PLBV46
XCL
MPMC
XCL
XPS CDMA
XPS CDMA
Device Under
Test (DUT)
PowerPC 440
Processor
MC
PPC440
MC DDR2
PLBV46
MDM
XPS INTC
XPS BRAM
XPS UART
Lite
MDM
Figure 27: Virtex-5 FX System
DS581_27_080309
DS581 September 16, 2009
www.xilinx.com
47
Product Specification