DS581 Datasheet, PDF (7/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
Table 1: XPS EPC IP Core Design Parameters (Contd)
Generic Feature/Description
Parameter Name
Allowable Values
Default
Value
VHDL
Type
G17
External peripheral base C_PRHx_
address
BASEADDR⁽⁴⁾
Valid address^(5,6)
User must
set
values⁽⁶⁾
std_logic
_vector
G18
External peripheral high C_PRHx_
address
HIGHADDR⁽⁴⁾
Valid address^(5,6)
User must
set
values⁽⁶⁾
std_logic
_vector
XPS EPC Peripheral Interface Parameters
G19
Support for access to
FIFO within the external
peripheral
C_PRHx_FIFO_
ACCESS⁽⁴⁾
0 = No support for the
external peripheral
FIFO access
1 = Access to FIFO
0
structures within the
external peripheral
device is supported
integer
External peripheral
C_PRHx_FIFO_
G20
FIFO offset from
peripheral base address
OFFSET^(4,8,9)
Any valid offset within
the base and high
address range
0
assigned to the
peripheral device
integer
G21
Address bus width of
peripherals
C_PRHx_AWIDTH⁽⁴⁾ 3 - 32
32
integer
G22
Data bus width of
peripherals
C_PRHx_DWIDTH⁽⁴⁾ 8, 16 or 32
32
integer
0 = No multiple cycles
on the peripheral
interface for single
Support for data width
PLB read or write
match when the
C_PRHx_DWIDTH_
cycle
G23
peripheral device data
width is less than the
MATCH^(4,10)
1 = Run multiple
0
PLB data width
cycles on the
peripheral interface
for single PLB read or
write cycle
integer
0 = External device is
G24 Peripheral access mode C_PRHx_SYNC^(1,4)
asynchronous
1 = External device is
1
synchronous
integer
G25 Peripheral bus type
C_PRHx_BUS_
MULTIPLEX⁽⁴⁾
0 = External device
has separate address
and data bus
1 = External device
0
has multiplexed
address and data bus
integer
XPS EPC Timing Parameters
DS581 September 16, 2009
www.xilinx.com
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Product Specification