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DS581 Datasheet, PDF (14/50 Pages) Xilinx, Inc – PLB interface with byte enable support
XPS External Peripheral Controller (EPC) v1.02a
Table 2: XPS EPC IP Core I/O Signal Description (Contd)
Port
Signal Name
Interface
Signal
Type
Initial
State
Description
PRH_Addr[0 : C_PRH_
P46 MAX_AWIDTH - 1](2)
EPC
O
-
External peripheral address bus
P47 PRH_ADS
External peripheral address
strobe in case of multiplexed
EPC
O
0
address and data bus.
Active high signal
P48
PRH_BE[0 : C_PRH_
MAX_DWIDTH/8 - 1]
EPC
O
-
External peripheral byte enables
P49 PRH_RNW
External peripheral read/write
EPC
O
1
signal for synchronous access
mode
P50 PRH_Rd_n
External peripheral read signal
EPC
O
1
for asynchronous access mode.
Active low signal
P51 PRH_Wr_n
External peripheral write signal
EPC
O
1
for asynchronous access mode.
Active low signal
P52 PRH_Burst
Burst cycle indication to external
EPC
O
0
peripheral.
Active high signal
P53 PRH_Rdy[0 : C_NUM_
PERIPHERALS - 1]
EPC
I
Peripheral ready signal. This
signal is used by the external
-
peripheral to extend the
transaction.
Active high signal
PRH_Data_I[0 :
P54 C_PRH_MAX_ADWIDTH - 1]
EPC
I
-
External peripheral input data
bus
P55 PRH_Data_O[0 :
C_PRH_MAX_ADWIDTH - 1]
EPC
O
-
External peripheral output data
bus
P56
PRH_Data_T[0 :
C_PRH_MAX_ADWIDTH - 1]
EPC
O
-
3-state control for external
peripheral output data bus
Notes:
1. PRH_Clk is utilized only when C_PRH_CLK_SUPPORT = 1 and the interface to the external peripheral is
synchronous.
2. External peripheral devices are considered as byte addressable irrespective of the data bus width.
Parameter - Port Dependencies
The dependencies between the XPS EPC design parameters and the I/O ports are shown in Table 3. The
width of the XPS EPC signals depend on some of the parameters. In addition, when certain features are
parameterized out of the design, the related logic will no longer be a part of the design. The unused
input signals and unrelated output signals are set to a specified value.
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DS581 September 16, 2009
Product Specification