DS581 Datasheet, PDF (22/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
C_PRHx_RDY_WIDTH < IPIF time out(128 PLB cycles). Starting from the falling edge of the
PRH_WR_n or, PRH_RD_n signal, the internal counter for C_PRHx_RDY_TOUT &
C_PRHx_RDY_WIDTH will start. The XPS EPC IP Core expects that the PRH_Rdy signal should
appear before any of these timer ends. If the PRH_Rdy doesn’t become active before the
C_PRHx_RDY_TOUT counter ends, then the XPS EPC IP Core will wait till the end of
C_PRHx_RDY_WIDTH counter. In case, PRH_Rdy becomes active then internal state machine will
proceed to complete the further process steps. If PRH_Rdy doesn’t become active even before the
C_PRHx_RDY_WIDTH ends, the XPS EPC IP Core will generate an error and terminate the
transaction. User can re-initiate the same transaction later on.
Figure 3 below shows the diagrammatic representation of how the async state machine reacts with the
PRH_Rdy signal. Please consider this figure as representation only. In actual design, there are some
dummy states added to meet the design requirements. In case of asynchronous reset to the core, all the
states will go to IDLE by default.
If the external peripheral device does not have a device ready signal, then the PRH_Rdy input of the
XPS EPC for that particular device must be tied to logic high.
Figure Top x-ref 3
Idle State
Non-Multiplexing Mode
Start State
Multiplexing Mode
Control Assert
Device Ready
Check
Buffer Period
Device Ready
Confirm Check
Device
No
Ready?
Yes
Control De-assert
Dummy State
(in case of read)
Device Ready
Check
Device Ready
Confirm Check
No _Device
Ready?
Yes
Address Strobe
Dummy State
Buffer Period
No
Yes
Multiplexed?
Control Assert
Yes
Data Width
Match = 1 ?
Data Width ^Yes
Match = 1 ?
No
Non-Multiplexed
Recovery Period
No
Multiplexed
Recovery Period
DS581_03_080309
Figure 3: Diagrammatic Representation of Async State Machine Flow
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DS581 September 16, 2009
Product Specification