DS581 Datasheet, PDF (35/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
Figure Top x-ref 19
Cycles
0 1 2 3 4 5 6 7 8 9 1011 12 13 1415 16 17 1819 20 2122 23 24 2527 2829 30 31 3233 34 35 3637 38 394041 42 4344 45 4647 48
SPLB_Clk
SPLB_Rst
PLB_type[0:2]
0
PLB_size[0:3]
0
PLB_ABus[0:31]
20000000
PLB_PAValid
PLB_RNW
PLB_BE[0:3]
F
PLB_wrDBus[0:31]
00000000
Sl_RdDbus[0:31]
04050607
PRH_CS_n
PRH_Addr
00
01
02
03
PRH_ADS
PRH_BE
01
PRH_Rdy
PRH_WR_n
PRH_Rd_n
PRH_Data
000
040
001
050
002
060
003
070
PRH_RNW
PRH_Burst
DS581_19_080309
Figure 19: Asynchronous Read Transactions to Device Memory When Bus is Multiplexed and Data
Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 20
Cycles
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
SPLB_Clk
SPLB_Rst
PLB_type[0:2]
0
PLB_size[0:3]
0
PLB_ABus[0:31]
20000000
PLB_PAValid
PLB_RNW
PLB_BE[0:3]
F
PLB_wrDBus[0:31]
04050607
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rdy
PRH_WR_n
PRH_RD_n
PRH_Data
PRH_RNW
PRH_Burst
00
040
01
02
01
050
060
03
070
DS581_20_080309
Figure 20: Asynchronous Write Transactions to Device Memory When Bus is Not Multiplexed and Data
Width Matching is Enabled
DS581 September 16, 2009
www.xilinx.com
35
Product Specification