DS581 Datasheet, PDF (38/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
Figure Top x-ref 25
Cycles
0 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 0 1 2 3 4 5 6 7 8 9 11 12 13 14
SPLB_Clk
SPLB_Reset
PLB_type[0:2]
0
PLB_size[0:3]
0
PLB_ABus[0:31]
20000004
20000004
PLB_PAValid
PLB_RNW
PLB_BE[0:3]
0F
0F
PLB_wrDBus[0:31]
04050607
Sl_RdDbus[0:31]
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_WR_n
PRH_Rd_n
PRH_Rdy
PRH_Data
PRH_RNW
PRH_Burst
04
04
0F
0F
Control signal active period is extended till internal time-out counter expires
04050607
DS581_25_080309
Figure 25: Asynchronous Write-Read Transactions to Device Memory When Bus is Not Multiplexed and
Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0). Please note that the external peripheral
device is not ready for communication and no PRH_Rdy comes.
Scenario When The External Device Is Not Ready For Transaction
In scenarios where, the XPS EPC IP Core has initiated the transaction, but the external peripheral in not
ready ( PRH_Rdy signal will not be activated), the control signals from the core will be extended till the
internal C_PRHx_RDY_WIDTH counter expires. The core completes the transaction with error signal
generation.
Target Technology
The target technology is an FPGA listed in the Supported Device Family field of the LogiCORE Facts
Table.
Device Utilization and Performance Benchmarks
Core Performance
Because the XPS EPC module will be used with other design modules in the FPGA, the utilization and
timing numbers reported in this section are estimates. When the XPS EPC module is combined with
other designs, the utilization of FPGA resources and timing of the XPS EPC IP Core design will vary
from the results reported here.
38
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DS581 September 16, 2009
Product Specification