DS581 Datasheet, PDF (48/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
Figure Top x-ref 28
MicroBlaze
Processor
MPMC
XPS CDMA XPS CDMA
Device Under
Test (DUT)
PLBV46
XPS BRAM XPS INTC
XPS GPIO
XPS UART
Lite
Figure 28: Spartan-3A System
MDM
DS581_28_080309
The target FPGA was then filled with logic to drive the LUT and BRAM utilization to approximately
70% and the I/O utilization to approximately 80%. Using the default tool options and the slowest speed
grade for the target FPGA, the resulting target F_MAX numbers are shown in Table 9.
Table 9: XPS EPC System Performance
Target FPGA
S3A700 -4
Target F_MAX (MHz)
90
V4FX60 -10
100
V5LXT50 -1
120
The target F_MAX is influenced by the exact system and is provided for guidance. It is not a guaranteed
value across all systems.
Specification Exceptions
N/A
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in
devices that are not defined in the documentation, if customized beyond that allowed in the product
documentation, or if changes are made to any section of the design labeled DO NOT MODIFY.
Reference Documents
The following documents contain information that may be required in understanding the XPS EPC IP
Core reference design:
1. DS583 XPS SYSACE (System ACE) Interface Controller
2. DS561 PLBv46 Slave Single
3. 10/100 Non-PCI Ethernet Single Chip MAC + PHY LAN91C111 Data Sheet, SMSC
4. EZ-Host(TM) Programmable Embedded USB Host/Peripheral Controller CY7C67300 Data Sheet,
Cypress Semiconductor
5. IBM CoreConnect 128-Bit Processor Local Bus: Architecture Specifications version 4.6
48
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DS581 September 16, 2009
Product Specification