DS581 Datasheet, PDF (26/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
Figure Top x-ref 6
External Reset
FPGA
PPC
XPS EPC
PRH_Clk
PRH_Rst
PRH_CS_n
PRH_ADS
PRH_ADDR[0:14]
PRH_BE[0:3]
PRH_RNW
PRH_Rdy
PRH_Rd_n
PRH_Wr_n
PRH_Burst
PRH_DATA[0:31]
VCC
External
Glue Logic
SMSC LAN91C111
LCLK
W/nR
Reset
nVLBUS
AEN
nCYCLE
nADS nRDYRTN
A[15:1] nDADACS
nLDEV
nBE[3:0] nSARDY
VCC
ARDY
nRd
nWR
D[31:0]
To System Interrupt Controller
INTRO
DS581_06_080309
Figure 6: SMSC LAN91C111 Connection to XPS EPC IP Core in Asynchronous Mode
External Glue Logic
Special attention must be given while interfacing the XPS EPC IP Core to the SMSC LAN91C111 in
asynchronous mode. The XPS EPC IP Core drives the PRH_BE active high while the SMSC LAN91C111
requires the input byte enable to be active low. To match this requirement, external glue logic is
required to invert the PRH_BE signals before they are interfaced with the byte enable signals of the
SMSC LAN91C111.
Synchronous Mode
Figure 7 illustrates the example for SMSC LAN91C111 connection to the XPS EPC IP Core in
synchronous VL Bus mode with non-multiplexed address and data buses. In synchronous mode, the
device requires an input clock source to the LCLK pin with a maximum operating frequency of 50MHz.
The local clock generated by the DCM for the peripheral interface must be routed to the LCLK input of
SMSC LAN91C111 and PRH_Clk of XPS EPC IP Core. When the device is accessed, PRH_RNW is used
as the control signal to indicate a read/write access. When PRH_RNW is high, it indicates a read
operation and when low, it indicates a write operation. The SMSC LAN91C111 uses nSRDY signal to
indicate the device readiness. This signal is connected to PRH_Rdy input of the XPS_EPC. As the
address and the data bus are not multiplexed, PRH_ADS will be driven low.
26
www.xilinx.com
DS581 September 16, 2009
Product Specification