DS581 Datasheet, PDF (29/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
Figure Top x-ref 8
FPGA
XPS EPC
PRH_Rst
PRH_Rdy
PRH_CS_n
PRH_Data_I[0:15]
PRH_Data_O[0:15]
PRH_Data_T[0:15]
PRH_ADS
PRH_RRNW
PRH_Burst
PRH_Rd_n
PRH_Wr_n
PRH_Addr[0:3]
XPS SYS ACE
SysACE_mpd_I[0:15] ^[15:0]
SysACE_mpd_O[0:15] ^[15:0]
SysACE_mpd_T[0:15] ^[15:0]
SysACE_mpwe
SysACE_mpoe
SysACE_MPA[0:6] ^[6:0]
SysACE_CEN
XPS
INTC
VCC
sysace_epc_data[15:0]
sysace_epc_rd_n
sysace_epc_wr_n
HPI interface
nCS
[D15:D0]
nRD
nWR
DM1B
DP1B
DM2A
DP2A
DM1A
DP1A
sysace_epc_a[1:0]
[A1:A0]
INT
TQFP144 SYSTEMACE
System ACE CompactFlash Controller
Compact
FLASH
DS581_08_080309
Figure 8: CY7C67300 USB Controller connection to XPS EPC in asynchronous mode
External Glue Logic
In the interface diagram example shown in Figure 8, the XPS EPC IP Core as well as the XPS SYSACE
share the interface for data, address and control lines on the board. This requires external multiplex
logic to be placed outside of IP cores in the FPGA. The XPS EPC IP Core control signals PRH_RD_n and
PRH_WR_n are muxed with the MEM_CEN and MEM_WEN signals of the XPS SYSACE. When
CY7C67300 USB Controller is accessed through the asynchronous mode, the rising edge of
sysace_epc_rd_n and sysace_epc_wr_n signals are used to control the read and the write operations
respectively. See the Reference Documents section for more information on XPS SYSACE.
Design Constraints
Timing Constraints
Timing constraints must be placed on the system clock and the peripheral clock, setting the frequency
to meet the bus timing requirements. An example is shown in Figure 9.
DS581 September 16, 2009
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Product Specification