DS581 Datasheet, PDF (36/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
Figure Top x-ref 21
Cycles
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
SPLB_Clk
SPLB_Rst
PLB_type[0:2]
0
PLB_size[0:3]
0
PLB_ABus[0:31]
20000000
PLB_PAValid
PLB_RNW
PLB_BE[0:3]
F
PLB_wrDBus[0:31]
00000000
Sl_RdDbus[0:31]
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rdy
PRH_WR_n
PRH_Rd_n
PRH_Data
PRH_RNW
PRH_Burst
00
040
01
02
01
050
060
04050607
03
070
DS581_21_080309
Figure 21: Asynchronous Read Transactions to Device Memory When Bus is Not Multiplexed and Data
Width Matching is Enabled
Figure Top x-ref 22
Cycles
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SPLB_Clk
SPLB_Rst
PLB_type[0:2]
0
PLB_size[0:3]
PLB_ABus[0:31]
PLB_PAValid
PLB_RNW
PLB_BE[0:3]
0
20000000
0F
PLB_wrDBus[0:31]
04050607
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rdy
PRH_WR_n
PRH_RD_n
PRH_Data
PRH_RNW
PRH_Burst
00
0F
000
04050607
DS581_22_080309
Figure 22: Asynchronous Write Transactions to Device Memory When Bus is Multiplexed and Data Width
Matching is Disabled
36
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DS581 September 16, 2009
Product Specification