DS581 Datasheet, PDF (6/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
Table 1: XPS EPC IP Core Design Parameters (Contd)
Generic Feature/Description Parameter Name Allowable Values
G3 PLB data width
C_SPLB_DWIDTH
32, 64, 128
G4
Selects point-to-point or
shared PLB topology
C_SPLB_P2P
0 = Shared Bus
Topology
G5
PLB Master ID Bus
Width
C_SPLB_MID_
WIDTH
log₂(C_SPLB_NUM_
MASTERS) with a
minimum value of 1
G6
Number of PLB Masters ^C_SPLB_NUM_
MASTERS
1 - 16
G7
Width of the Slave Data C_SPLB_NATIVE_
Bus
DWIDTH
32
G8
PLB supports burst
transactions
C_SPLB_SUPPORT_B
URSTS
0
XPS EPC Interface Parameters
G9 PLB clock period
C_SPLB_CLK_
PERIOD_PS⁽¹⁾
Integer number of
picoseconds
C_PRH_CLK_
G10 Peripheral clock period _{PERIOD_PS}
Integer number of
picoseconds
G11 Number of peripherals ^C_NUM_
1- 4
PERIPHERALS
G12
Maximum of address
bus width of all external
peripherals
C_PRH_MAX_
AWIDTH
3 - 32
G13
Maximum of data bus
width of all external
peripherals
C_PRH_MAX_
DWIDTH
8, 16 , 32
Maximum of data bus
width of all peripherals
G14
and address bus with of C_PRH_MAX_
peripherals employing ADWIDTH⁽²⁾
address/data
multiplexing
8 - 32
C_PRH_CLK_
G15
Peripheral clock support _SUPPORT(1)
0 = Peripheral device
interface operates at
the PLB clock
1 = Peripheral device
interface operates at
external peripheral
clock
G16 PLB burst support
C_PRH_BURST_
SUPPORT⁽³⁾
0 = No burst support
from PLB
XPS EPC Peripheral Address Space
Default
Value
32
0
1
1
32
0
10000
20000
1
32
32
32
0
0
VHDL
Type
integer
integer
integer
integer
integer
integer
integer
integer
integer
integer
integer
integer
integer
integer
6
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DS581 September 16, 2009
Product Specification