DS581 Datasheet, PDF (27/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
The following parameter settings apply for the connections shown in Figure 7.
• C_PRH_CLK_SUPPORT = 1
• C_PRH0_AWIDTH = 16
• C_PRH0_DWIDTH = 32
• C_PRH0_SYNC = 1
• C_PRH0_DWIDTH_MATCH = 0
• C_PRH0_BUS_MULTIPLEX = 0
Figure Top x-ref 7
FPGA
XPS EPC
PRH_Clk
PRH_Rst
PRH_CS_n
PRH_ADS
PRH_ADDR[0:14]
PRH_BE[0:3]
PRH_RNW
PRH_Rdy
PRH_Rd_n
PRH_Wr_n
PRH_Burst
PRH_DATA[0:31]
Digital
Clock
Manager
External Reset
SMSC LAN91C111
LCLK
nRd
Reset
nWR
AEN nDADACS
nADS
nLDEV
A[15:1]
ARDY
nBE[3:0] nVLBUS
W/nR
nSRDY
D[31:0]
VCC
GND
External
Glue Logic
nCYCLE
nRDYRTN
To System Interrupt Controller
INTRO
DS581_07_080309
Figure 7: SMSC LAN91C111 Connection to XPS EPC IP Core in Synchronous Mode
External Glue Logic
The SMSC LAN91C111 device requires two inputs, nCYCLE and nRDYRTN, to control synchronous
operation. The definition of these signals is outside the scope of this document and can be found in the
documents listed in the Reference Documents section. The nCYCLE and nRDYRTN signals are
generated in external glue logic. nCYCLE may be generated from PRH_CS_n and is driven low for a
single clock cycle on a high to low transition on PRH_CS_n. nRDYRTN is simply the registered value of
the nSRDY signal.
In case of synchronous multiplexing mode, the generation of nCYCLE signal is little different. The
PRH_CS_n signal will be generated twice from the core, first during the address phase and second time
during the data phase. User should take care while writing the logic for nCYCLE signal generation in
external glue logic. The nCYCLE should be generated in data phase when there is PRH_CS_n asserted
and PRH_ADS is not present.
Design Considerations
When the XPS EPC IP Core is interfaced to the SMSC LAN91C111 with data width match enabled
(C_PRHx_DWIDTH_MATCH = 1) and the internal SRAM of the peripheral is being accessed, the
DS581 September 16, 2009
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Product Specification