DS581 Datasheet, PDF (23/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
Peripheral Data Bus Mapping
The peripheral data bus (PRH_Data) uses big endian bit labelling (i.e. bit-0 is Most Significant Bit (MSB)
and bit-31 is Least Significant Bit (LSB) for a 32-bit bus) and is sized according to the
C_PRH_MAX_ADWIDTH parameter. Peripherals that have smaller widths should connect to this bus
starting at bit 0 (MSB). For example, if three external devices are present in the system with data bus
width of 8-bit, 16-bit and 32-bit, the 8-bit device should connect to PRH_Data[0 : 7], the 16-bit wide
peripheral should connect to PRH_Data[0 : 15] and the 32-bit peripheral should connect to PRH_Data
[0 : 31].
The bit and byte labeling for the big endian data types is shown in Figure 4.
Figure Top x-ref 4
Byte address
n
n+1
n+2
Word
n+3
Byte label
0
1
2
3
Byte significance MS Byte
LS Byte
Bit label 0
31
Bit significance MS Bit
LS Bit
Byte address
n
Byte label
0
Byte significance MS Byte
Bit label 0
Bit significance MS Bit
Halfword
n+1
1
LS Byte
15
LS Bit
Byte address
n
Byte
Byte label
0
Byte significance MS Byte
Bit label 0
7
Bit significance MS Bit LS Bit
Figure 4: XPS EPC Big Endian Data Type
DS581_04_080309
Unsupported Features
Many peripheral devices have the device specific input/output ports such as status, remote reset,
remote wakeup, interrupts etc. The XPS EPC IP Core does not have any provision to support these
device specific input/output ports. Therefore, if the external device has any such device specific ports,
then these input/output ports may be connected directly to system general purpose input output
controller or to the system interrupt controller. If the external device has interrupt capability, then the
interrupt outputs of the external device should be connected directly to the system interrupt controller.
Many peripheral devices support DMA capability. However, the XPS EPC IP Core is a PLB slave device
and therefore does not support DMA operations from the external peripheral devices.
Current version of the XPS EPC IP Core does not support burst transactions to/from the PLB. So the
parameter C_PRH_BURST_SUPPORT must be always assigned to ’0’.
DS581 September 16, 2009
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Product Specification