DS581 Datasheet, PDF (3/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
Figure Top x-ref 2
Processor Local Bus (PLB)
Address
Bus
Data
Bus
XPS EPC
PLB Interface Module
IPIC Control Signals
Address
Generation
IPIC IF Decode
SPLB_Clk/
PRH_Clk
Sync
Control
Data
Steer
Control Signal
Generation
Async Control
Cycle Time
Generation
Address/
Data Mux
Access
Mux
Control
Signal Mux
Peripheral
Address Bus
Peripheral
Data Bus
Peripheral
Control Signals
DS581_02_080309
Figure 2: XPS EPC Block Diagram
The XPS EPC core consists of:
• The PLB Interface Module: This module provides the address decoding logic and necessary
interface between PLB and XPS EPC core signals.
• The IPIC IF Decode module: This module provides decoding of IPIC signals of PLB Interface
Module and synchronization of control signals.
• The Sync Control module: This module implements the state machine which controls the
synchronous interface.
• The Async Control module: This module implements the state machine which controls the
asynchronous interface including the asynchronous timing parameters.
• The Data Steer module: This module provides the data bus width matching and data steering logic.
• The Address Generation module: This module provides the generation of the lower address bits.
DS581 September 16, 2009
www.xilinx.com
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Product Specification