DS581 Datasheet, PDF (32/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
Figure Top x-ref 13
Cycles
0 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18
SPLB_Clk
SPLB_Rst
PLB_type[0:2]
0
PLB_size[0:3]
0
PLB_ABus[0:31]
20000000
PLB_PAValid
PLB_RNW
PLB_BE[0:3]
F
PLB_wrDBus[0:31]
01020304
PRH_CS_n
PRH_Addr
00
01 02 03
PRH_ADS
PRH_BE
01
PRH_Burst
PRH_Rdy
PRH_RNW
PRH_Daat
01
02 03 04
DS581_13_080309
Figure 13: Synchronous Write Transactions to Device Memory When Bus is Not Multiplexed and Data
Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 14
Cycles
01
2
3
4
5
6
7
9
10
11
12
13
14
SPLB_Clk
SPLB_Rst
PLB_type[0:2]
0
PLB_size[0:3]
0
PLB_ABus[0:31]
20000000
PLB_PAValid
PLB_RNW
PLB_BE[0:3]
F
PLB_wrDBus[0:31]
00000000
Sl_RdDbus[0:31]
01020304
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Burst
PRH_Rdy
PRH_RNW
PRH_Data
00
01
01
02
03
01
02
03
04
DS581_14_080309
Figure 14: Synchronous Read Transactions to Device Memory When Bus is Not Multiplexed and Data
Width Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
32
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DS581 September 16, 2009
Product Specification