DS581 Datasheet, PDF (5/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
Similarly, for a read cycle, when the external device indicates it is ready to complete the transaction, the
data on the peripheral data bus (PRH_Data[0 : 7]) is internally registered as the first byte to be
presented to PLB data bus (PLB_wrDBus[0 : 7]) followed by initiation of new read cycle on the
peripheral interface. The second read access on the peripheral data bus (PRH_Data[0 : 7]) is internally
registered as the second byte to be presented to PLB data bus (PLB_wrDBus[8 : 15]) and so on. When all
four bytes are read from the external device an acknowledge is generated to the PLB Interface Module
to indicate that the data is ready to be transferred to PLB data bus.
When support for data width match is enabled for any of the external devices, then the access to that
device should respect data alignment i.e a half word access should be aligned to a 16-bit boundary and
a word access should be aligned to a 32-bit boundary.
Access Mux Module
The interface to the external peripherals supports both multiplexed and non-multiplexed address and
data bus to the external devices. The Access Mux Module controls the multiplexing of the peripheral
address and data buses based on the parameter C_PRHx_BUS_MULTIPLEX. If C_PRHx_BUS_
MULTIPLEX = 1, the address and the data bus are multiplexed and presented to the corresponding
external device on PRH_Data bus. The address will be valid on the PRH_Data bus as long as the
address strobe is active (PRH_ADS). This access will be performed in two phases (address phase and
data phase). The data phase will be followed by the address phase. If C_PRHx_BUS_MULTIPLEX = 0,
then the address and the data are presented to the device on separate buses (PRH_Addr bus and
PRH_Data bus) and the access cycle will contain only one phase.
XPS EPC IP Core Design Parameters
To allow the user to create the XPS EPC that is uniquely tailored for the user’s system, certain features
can be parameterized in the XPS EPC design. Some of these parameters control the interface to the PLB
while others control the interface to the peripheral devices. This allows the user to have a design that
utilizes only the minimum resources required by the system and runs at the best possible performance.
The features that are parameterizable in the XPS EPC core are as shown in Table 1.
Table 1: XPS EPC IP Core Design Parameters
Generic Feature/Description Parameter Name Allowable Values
G1 Target FPGA family
G2 PLB address width
System Parameter
C_FAMILY
spartan3a,
aspartan3a,
spartan3, aspartan3,
spartan3e,
aspartan3e,
spartan3adsp,
aspartan3adsp,
spartan6, virtex4,
qvirtex4, qrvirtex4,
virtex5, virtex5fx,
virtex6, virtex6cx
PLB Parameters
C_SPLB_AWIDTH
32
Default
Value
virtex5
32
VHDL
Type
string
integer
DS581 September 16, 2009
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Product Specification