DS581 Datasheet, PDF (15/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
Table 3: XPS EPC IP Core Parameter - Port Dependencies
Generic
or Port
Name
Affects Depends
Description
Design Parameters
The PLB data width parameter affects the number
P7,
G3 C_SPLB_DWIDTH
P10, P33
-
of byte enables configured for the PLB data bus,
width of the PLB data bus and the width of the PLB
slave read data bus
C_SPLB_MID_
Affects the number of bits required for the
G5
WIDTH
P5
G6
PLB_masterID input bus for slave devices. This
value is equal to log₂(C_SPLB_NUM_MASTERS)
G6
C_SPLB_NUM_
MASTERS
P36, P37,
P38, P42
-
Affects the number of PLB masters
The number of peripherals in the system
G11
C_NUM_
PERIPHERALS
P45, P53
-
determines the number of chip select signals
driven and the number of device ready inputs
decoded by the PLB external peripheral controller
G12 ^C_PRH_MAX_
P46
AWIDTH
The width of the peripheral address bus is set to
-
the maximum of address bus width of all peripheral
devices
G13
C_PRH_MAX_
DWIDTH
P48
The number of byte enables for the peripheral data
-
bus is determined by the maximum of data bus
width of the peripheral devices
The width of the peripheral input data bus,
peripheral output data bus and the peripheral
C_PRH_MAX_
G14 _ADWIDTH
P54,
P55, P56
-
output data bus 3-state control are determined by
the maximum of data bus width of all peripherals
and the address bus width of peripherals
employing address / data bus multiplexing
G15 ^C_PRH_CLK_
P43
If C_PRH_CLK_SUPPORT = 0 then all external
-
devices operate on SPLB clock. The input
SUPPORT
PRH_Clk must be driven high externally
G23
C_PRHx_DWIDTH
_MATCH
P52
If the device is configured for synchronous mode
with data width matching enabled then PRH_Burst
-
will be driven high until all but the last byte of data
is flushed to the device. For asynchronous mode
and synchronous mode with data width match
disabled, PRH_Burst is driven low.
DS581 September 16, 2009
www.xilinx.com
15
Product Specification