DS581 Datasheet, PDF (24/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
XPS EPC IP Core External Peripheral Connections
The XPS EPC IP Core interface to the external device is based upon the width of the PLB data bus,
address and data width of the peripheral subsystem, number of peripherals in the system,
address/data multiplex support, mode of operation (synchronous or asynchronous) and if
synchronous device, the operating clock for the synchronous data path.
Determining Address and Data Width
The address bus width of the peripheral subsystem is the maximum width of the address bus of all
peripheral devices connected to the XPS EPC IP Core . If all devices employ non-multiplexed address
and data bus, the data bus width of the peripheral subsystem is the maximum of the data bus width of
all external devices. If any of the devices are configured for multiplexed address and data bus, then the
data bus width of the peripheral subsystem should be set as the maximum of the data bus and the
address bus of the device(s) employing a multiplexed address and data bus.
Endian Considerations
XPS EPC has big endian style address and data bits; for example, D0 is MSB and D31 is LSB. Please
make sure that the external peripheral interface is properly assigned with correct ordering of the bus.
Clock Generation
When connecting to a synchronous external device, the XPS EPC IP Core may operate either on the PLB
clock (SPLB_Clk) or on a peripheral clock (PRH_Clk). The operating clock for the synchronous
interface is based on the generic C_PRH_CLK_SUPPORT. If C_PRH_CLK_SUPPORT = 1, the
peripheral clock is used else the PLB clock is used. The external devices connected to the XPS EPC IP
Core will determine the operating frequency of the peripheral clock. The minimum of the operating
frequencies of various devices connected to XPS EPC IP Core should be used as the operating
frequency of the peripheral clock (PRH_Clk).
Figure 5 illustrates a block diagram of one of the methods for generating a device specific clock source
using two DCMs. The DCM modules are located within the FPGA but are external to the XPS EPC IP
Core. An external clock source is used to generate the XPS clock (SPLB_Clk) to the XPS EPC. The device
clock source (PRH_Clk) is also generated from the same DCM (DCM0) using the CLKFX output and
must be routed on the board to be fed back to the FPGA. The parameters of DCM0 like
C_CLKFX_MULTIPLY and C_CLKFX_DIVIDE should be set according to the required frequency
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DS581 September 16, 2009
Product Specification