DS581 Datasheet, PDF (12/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
XPS EPC IP Core I/O Signals
The XPS EPC IP Core I/O signals are listed and described in the Table 2.
Table 2: XPS EPC IP Core I/O Signal Description
Port
Signal Name
Interface
Signal
Type
Initial
State
Description
System Signals
P1 SPLB_Clk
PLB
I
-
PLB clock
P2 SPLB_Rst
PLB
I
-
PLB reset. Active high
PLB Slave Interface Input Signals
P3 PLB_ABus[0 : 31]
PLB
I
-
PLB address bus
P4 PLB_PAValid
PLB
I
-
PLB primary address valid
P5
PLB_masterID[0 :
C_SPLB_MID_WIDTH - 1]
PLB
I
-
PLB current master identifier
P6 PLB_RNW
PLB
I
-
PLB read not write
P7
PLB_BE[0 :
(C_SPLB_DWIDTH/8) - 1]
PLB
I
-
PLB byte enables
P8 PLB_size[0 : 3]
PLB
I
-
PLB size of requested transfer
P9 PLB_type(0 : 2]
PLB
I
-
PLB transfer type
P10
PLB_wrDBus[0 :
C_SPLB_DWIDTH - 1]
PLB
I
-
PLB write data bus
Unused PLB Slave Interface Input Signals
P11 PLB_UABus[0 : 31]
PLB
I
-
PLB upper address bits
P12 PLB_SAValid
PLB
I
-
PLB secondary address valid
P13 PLB_rdPrim
PLB
I
-
PLB secondary to primary read
request indicator
P14 PLB_wrPrim
PLB
I
-
PLB secondary to primary write
request indicator
P15 PLB_abort
PLB
I
-
PLB abort bus request
P16 PLB_busLock
PLB
I
-
PLB bus lock
P17 PLB_MSize[0 : 1]
PLB
I
-
PLB data bus width indicator
P18 PLB_lockErr
PLB
I
-
PLB lock error
P19 PLB_wrBurst
PLB
I
-
PLB burst write transfer
P20 PLB_rdBurst
PLB
I
-
PLB burst read transfer
P21 PLB_wrPendReq
PLB
I
-
PLB pending bus write request
P22 PLB_rdPendReq
PLB
I
-
PLB pending bus read request
P23 PLB_wrPendPri[0 : 1]
PLB
I
-
PLB pending write request
priority
12
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DS581 September 16, 2009
Product Specification