DS581 Datasheet, PDF (30/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
Figure Top x-ref 9
Following constraint must be placed on the system clock:
NET SPLB_Clk TNM_NET = SPLB_Clk;
TIMESPEC TS_SPLB_Clk = PERIOD SPLB_Clk 10 ns HIGH 50%;
If C_PRH_CLK_SUPPORT=1, then the following constraint must be placed on the peripheral clock:
NET PRH_Clk TNM_NET = PRH_Clk;
TIMESPEC TS_PRH_Clk = PERIOD PRH_Clk 20 ns HIGH 50%;
Figure 9: XPS EPC Timing Constraints
DS581_09_080309
Design Implementation
Timing Diagrams
The timing diagrams in the figures below show various PLB transactions and the resulting access
cycles on the peripheral interface. Timing diagrams are not shown for all possible combinations of
generics and the resulting access cycles. However, the timing diagrams shown are sufficient for the
basic understanding of various access cycles supported by the XPS EPC IP Core .
Figure Top x-ref 10
Cycles
0
SPLB_Clk
SPLB_Reset
PLB_type[0:2]
PLB_size[0:3]
PLB_ABus[0:31]
PLB_PAValid
PLB_RNW
PLB_BE[0:3]
PLB_wrDBus[0:31]
Sl_RdDbus[0:31]
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Burst
PRH_Rdy
PRH_RNW
PRH_Daat
1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 0 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17
20000004
0
0
20000004
F
04050607
04
F
F
04050607
04
F
04050607
04050607
DS581_10_080309
Figure 10: Synchronous Write-Read Transactions to Device Memory When Bus is not Multiplexed and
Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0), assuming the peripheral device is ready
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DS581 September 16, 2009
Product Specification