DS581 Datasheet, PDF (4/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
• The Access Mux module: This module provides the multiplexing of address, data and other control
signals.
A detailed description of the above modules is provided below.
IPIC IF Decode Module
The IPIC IF Decode module implements the interface to the PLB. It also configures the EPC CORE and
interfaces to the Async Control module and Sync Control module by driving the necessary control
signals based on user parameter settings.
Sync Control and Async Control Modules
In Figure 2 the Sync Control and Async Control Modules depict the synchronous and asynchronous
paths of the EPC CORE. This ensures that the read and write accesses to the external device(s) adheres
to the specific timing parameters defined for the external device(s). Implementation of the Sync Control
and Async Control modules is dependent on the parameter C_PRHx_SYNC. If synchronous and
asynchronous external peripheral devices exist simultaneously then both the Sync Control and Async
Control modules will be implemented.
The Sync Control Module operates either on the PLB clock (SPLB_Clk) or on the external peripheral
clock (PRH_Clk) depending on the generic C_PRH_CLK_SUPPORT. If C_PRH_CLK_SUPPORT = 1,
then the Sync Control module operates on external device peripheral clock (PRH_Clk) that is different
from the PLB clock. If more than one device is synchronous, then the frequency for the PRH_Clk should
be chosen as the minimum of the operating frequencies of those devices. The IPIC control signals that
are inputs to the Sync Control module are synchronized to the PRH_Clk in the IPIC IF Decode module
to indicate the start of a transaction. Similarly, the control signals from the Sync Control module to the
IPIC interface such as data acknowledge are synchronized to the PLB clock in the IPIC IF Decode
module. If C_PRH_CLK_SUPPORT = 0, the Sync Control module operates on the PLB clock and the
IPIC Decode module interface does not perform synchronization of control signals.
The Async Control Module operates on the PLB clock only. This module generates the control signals
to the initiate read and write access cycles to the external peripheral device based on the asynchronous
timing parameters set by the user.
Data Steer and Address Generation Modules
The data bus of the external device must be less than or equal to the PLB data width and may be 8-bit,
16-bit or 32-bit. When the width of the external peripheral data bus is less than that of PLB and if
C_PRHx_DWIDTH_MATCH = 1 for a particular device, then the Data Steer Module will generate
multiple read or write cycles to the external device to match a single access on the PLB.
In order to map a single 32-bit PLB access to multiple 8-bit or 16-bit accesses, the lower bits of the
address bus are internally generated within the Address Generation Module to provide the correct
address to the external peripheral device. The address bus increments as each transaction completes.
For example, if the external device is 8-bit wide, then four read or write cycles to the device will be
performed in order to match a single 32-bit read or write transaction of PLB. For a write cycle, the first
byte of the PLB data bus (PLB_wrDBus[0 : 7]) is presented on the peripheral data bus (PRH_Data[0 : 7]).
When the external device accepts the transaction, a new write cycle is generated and the second byte of
the PLB data bus (PLB_wrDBus[8 : 15]) is presented on the peripheral data bus (PRH_Data[0 : 7]) and
so on. When the last byte of the PLB data bus (PLB_wrDBus[24 : 31]) is accepted by the peripheral, the
data acknowledge signal is generated and send to the PLB Interface Module to indicate that the access
is complete on the peripheral interface.
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DS581 September 16, 2009
Product Specification