DS581 Datasheet, PDF (37/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
Figure Top x-ref 23
Cycles
SPLB_Clk
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SPLB_Rst
PLB_type[0:2]
0
PLB_size[0:3]
0
PLB_ABus[0:31]
20000000
PLB_PAValid
PLB_RNW
PLB_BE[0:3]
F
PLB_wrDBus[0:31]
04050607
Sl_RdDbus[0:31]
04050607
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Rdy
PRH_RD_n
PRH_WR_n
PRH_Data
PRH_RNW
PRH_Burst
00
0F
000
04050607
DS581_23_080309
Figure 23: Asynchronous Read Transactions to Device Memory When Bus is Multiplexed and Data Width
Matching is Disabled
Figure Top x-ref 24
Cycles
0 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 0 1 2 3 4 5 6 7 8 9 11 12 13 14
SPLB_Clk
SPLB_Reset
PLB_type[0:2]
0
PLB_size[0:3]
0
PLB_ABus[0:31]
20000004
20000004
PLB_PAValid
PLB_RNW
PLB_BE[0:3]
0F
0F
PLB_wrDBus[0:31]
04050607
Sl_RdDbus[0:31]
PRH_CS_n
04050607
PRH_Addr
04
04
PRH_ADS
PRH_BE
0F
0F
PRH_WR_n
PRH_Rd_n
PRH_Rdy
PRH_Data
04050607
04050607
PRH_RNW
PRH_Burst
DS581_24_080309
Figure 24: Asynchronous Write-Read Transactions to Device Memory When Bus is Not Multiplexed and
Data Width Matching is Disabled (C_PRH_CLK_SUPPORT = 0). Please note the delayed response of
PRH_Rdy signal.
DS581 September 16, 2009
www.xilinx.com
37
Product Specification