DS581 Datasheet, PDF (33/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
Figure Top x-ref 15
Cycles
0 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18
SPLB_Clk
SPLB_Rst
PLB_type[0:2]
0
PLB_size[0:3]
0
PLB_ABus[0:31]
20000000
PLB_PAValid
PLB_RNW
PLB_BE[0:3]
0F
PLB_wrDBus[0:31]
01020304
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Burst
PRH_Rdy
PRH_RNW
PRH_Data
00
0F
00
01020304
DS581_15_080309
Figure 15: Synchronous Write Transactions to Device Memory When Bus is Multiplexed and Data Width
Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 16
Cycles
0 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18 19
SPLB_Clk
SPLB_Rst
PLB_type[0:2]
0
PLB_size[0:3]
0
PLB_ABus[0:31]
20000000
PLB_PAValid
PLB_RNW
PLB_BE[0:3]
0F
PLB_wrDBus[0:31]
00000000
Sl_RdDbus[0:31]
01020304
PRH_CS_n
PRH_Addr
PRH_ADS
PRH_BE
PRH_Burst
PRH_Rdy
PRH_RNW
PRH_Data
00
0F
00
01020304
DS581_16_080309
Figure 16: Synchronous Read Transactions to Device Memory When Bus is Multiplexed and Data Width
Matching is Disabled (C_PRH_CLK_SUPPORT = 0)
DS581 September 16, 2009
www.xilinx.com
33
Product Specification