DS581 Datasheet, PDF (21/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
Table 4: Example of Timing Ranges for XPS EPC IP Core in Asynchronous Mode of Operation
Parameter Name
Timing parameter’s range
C_PRHx_RDY_TOUT
10000^{(set 1)}
50000^{(set 2)}
60000^{(set 3)}
C_PRHx_RDY_WIDTH
50000
100000
120000
Note:
1. Please note that the above range of timing parameters (set 1) are used for internal device utilization and while
testing on USB and LAN. While using the above parameters care had been taken that all parameters of same
set are used.
2. Please note that the above timing sets (set 2 and set 3) are just an example of how the timing parameters can
be given to XPS EPC IP Core. The user can have different timing parameter values as per the targeted
device’s data sheet. In such cases, please note the calculation given above.
FIFO Transactions
When C_PRHx_FIFO_ACCESS = 1, the XPS EPC IP Core supports access to FIFO’s within the
external peripheral devices. When the FIFO within the external device is accessed, then the peripheral
address bus (PRH_Addr) must remain constant representing the FIFO address within the address
range assigned to the peripheral device. When data width matching is enabled and the access
corresponds to the FIFO, the XPS EPC IP Core does not increment the peripheral address (PRH_Addr)
bus.
Abnormal Terminations
If PRH_Rdy is de-asserted for more than the maximum period as specified by C_PRHx_RDY_WIDTH
then the XPS EPC terminates the current access to the external device and signals an error to the PLB
master by asserting either Sl_MWrErr or Sl_MRdErr on the PLB. Similarly, when the PLB master
terminates the current access (master abort on the PLB), XPS EPC terminates the access to the external
device immediately. In both cases, the access to the external device is terminated abnormally. Therefore,
the external device may be in an indeterminate state and the exceptions should be handled
appropriately at the system level.
Interrupt Handling
If the external device has interrupt capability, then the interrupt outputs of the external device should
be connected directly to the system interrupt controller.
Device Ready Signal (PRH_Rdy Signal)
The XPS EPC IP Core read/write access cycles are executed only when the external device assert the
device ready signal (PRH_Rdy).
As the PRH_Rdy signal becomes active, this indicates that the peripheral device is ready for
communication. Once the PRH_Rdy goes active, it is expected that it will remain in the same active
state till that particular transaction is completed by the XPS EPC IP Core. Please note that, if the XPS
EPC IP Core is implemented with data width match enabled, then the activeness of the PRH_Rdy
signal will always be checked for every transaction, regardless of it being active throughout the
transaction.
User should refer to the data sheet of the external peripheral, to define the value of PRH_Rdy time
period i.e. C_PRHx_RDY_TOUT parameter value should be filled based on the above information. It is
also expected that the user will provide maximum waiting period for PRH_Rdy signal. This waiting
period will be indicated by C_PRHx_RDY_WIDTH parameter. The C_PRHx_RDY_TOUT parameter
value should be less than the C_PRHx_RDY_WIDTH parameter value. The C_PRHx_RDY_WIDTH
time period should be lower than the PLB IPIF time out value i.e. C_PRHx_RDY_TOUT <
DS581 September 16, 2009
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Product Specification