DS566 Datasheet, PDF (9/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
Note: This PLB Master follows the IBM CoreConnect convention of left-to-right bit ordering and
Big Endian byte ordering.
Figure Top x-ref 4
0ns
clk
sof_n
sop_n
eop_n
eof_n
src_rdy_n
dst_rdy_n
d[0:63]
rem[0:7]
dst_dsc_n
src_dsc_n
100ns
200ns
300ns
400ns
500ns
600ns
700ns
800ns
0 123
4
5 6 7 8 9 10 11 12 13 14 15
SOP REM
DS566_04_033009
Figure 4: Basic LocalLink Data Transfer
I/O Signals
The PLBV46 Master signals are listed and described in Table 1.
Table 1: PLBV46 Master I/O Signal Description
Signal Name
Interface Signal Type Init Status
Description
System Signals
MPLB_clk
PLB System
Input
Synchronization clock for
the PLB Interface
MPLB_Rst
PLB System
Input
Master Reset for the PLB
Interface (Active high)
MD_Error
Sideband
Signal
Output
Master Detected Error
output. Asserted active
’0’
high when Master
encounters an error
condition. Cleared by
MPLB_Rst assertion.
PLB Master Request Signals
M_request
PLB Bus
Output
’0’
See table note 1.
M_priority
PLB Bus
Output
all ’0’
See table note 1.
M_buslock
PLB Bus
Output
’0’
See table note 1.
M_RNW
PLB Bus
Output
’0’
See table note 1.
M_BE(0 : C_MPLB_DWIDTH/8-1) PLB Bus
Output
all ’0’
See table note 1.
M_MSize(0 : 1)
PLB Bus
Output
all ’0’
See table note 1.
M_size(0 : 3)
PLB Bus
Output
all ’0’
See table note 1.
M_type(0 : 2)
PLB Bus
Output
all ’0’
See table note 1.
M_TAttribute(0:15)
M_lockErr ⁽²⁾
PLB Bus
PLB Bus
Output
Output
all ’0’
’0’
See table note 1.
See table note 1.
DS566 April 24, 2009
www.xilinx.com
9
Product Specification