DS566 Datasheet, PDF (38/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
Reference Documents
1. IBM CoreConnect 128-Bit Processor Local Bus, Architectural Specification (v4.6).
2. Xilinx SP026 PLBV46 Interface Simplifications
3. Xilinx SP006 LocalLink Interface Specification.
Revision History
Date
07/17/07
7/28/08
4/24/09
Version
1.0
1.2
1.3
Revision
Initial Xilinx release.
Added QPro Virtex-4 Hi-Rel and QPro Virtex-4 Rad Tolerant FPGA support.
Replaced references to supported device families and tool name(s) with hyperlink to
PDF file.
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www.xilinx.com
DS566 April 24, 2009
Product Specification