DS566 Datasheet, PDF (19/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
Table 1: PLBV46 Master I/O Signal Description
Signal Name
Interface Signal Type Init Status
Description
Bus2IP_MstWr_Cmd_TImeout
IP Write
Command
Status
Reply Intfc.
Output
This active high signal
indicates that the Master
has received a PLB
’0’
address phase Timeout
indication during the
course of executing the
requested write operation.
Bus2IP_MstWr_Length_is_Zero
IP Write
Command
Status
Reply Intfc.
Output
This active high signal
indicates that the data
transferred during the
’0’
Write Operation was
limited by the
IP2Bus_MstWr_Length
qualifier.
IP Client Write LocalLink I/O Signals
IP2Bus_MstWr_clk
IP Write
LocalLink
Intfc.
Input
The clock used to
synchronize the User IP
and the Write interface
when an asynchronous
Write FIFO is being
utilized. This signal is
ignored when a
synchronous or SRL Write
FIFO has been specified.
IP2Bus_MstWr_sof_n
IP Write
LocalLink
Intfc.
Input
Active low signal
indicating the Start Of
Frame for the requested
Write data packet.
IP2Bus_MstWr_eof_n
IP Write
LocalLink
Intfc.
Input
Active low signal
indicating the End Of
Frame for the requested
Write data packet.
IP2Bus_MstWr_sop_n
IP Write
LocalLink
Intfc.
Input
Active low signal
indicating the Start Of
Payload for the requested
read data packet. This
signal is ignored by the
Master.
IP2Bus_MstWr_eop_n
IP Write
LocalLink
Intfc.
Input
Active low signal
indicating the End Of
Payload for the requested
read data packet. An EOP
delimiter is required when
a LocalLink footer is
needed for the SG
operations. This signal is
ignored by the Master.
DS566 April 24, 2009
www.xilinx.com
19
Product Specification