DS566 Datasheet, PDF (31/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
An unaligned start condition will cause the Master to calculate and submit a single data beat PLB write
request for the unaligned starting data bytes. The Write Controller then calculates and requests write
burst transfers using the full data bus width until completed. If an unaligned end condition is detected,
the Write Controller will initiate PLB Burst transfers of the full data bus width until the last data beat.
For the last data beat, the Write Controller will calculate and submit a single data beat PLB write
request for the remaining unaligned starting data bytes. Thus, a general unaligned burst transfer
request may be required to be mechanized on the PLB by the Write Controller as a starting single beat,
a series of bus-width bursts, and then ending with a single data beat
Short write burst requests are also automatically converted. For example, a write request for Fixed
Length burst type may be requested via the Write Command interface and the associated Length and
starting address values may be such that the transfer cannot be completed with burst transfer protocol
on the PLB due to insufficient length. The Write Controller will automatically convert to single data
beat requests on the PLB to complete the transfer.
The following rules must be used for the relationship between the IP2Bus_MstWr_Addr and the
IP2Bus_MstWr_rem when an unaligned starting condition must be specified for a Fixed Length Burst.
The User may use any one of the three relationships.
1. The starting address and the first valid byte indicated by the REM on the first data beat of the write
must point to the same byte position,
2. or the starting REM can indicate the first valid byte of the transfer and the IP2Bus_MstWr_Addr
indicates the aligned address of the data beat containing the first valid byte,
3. or the REM value indicates all bytes of the data beat are valid and the User supplied address on the
IP2Bus_MstWr_Addr indicates where the first byte will be written.
Do not mix an unaligned starting address with an unaligned REM where the two do not point to the
same byte position. The unaligned REM will override the specified starting address and can lead to
data being written to an address that is before the starting address specified in the
IP2Bus_MstWr_Addr input.
IP Master Bus Locking
The PLB Bus Locking feature is not supported by this Master.
PLB Master Interface Transaction Timing
This section of the document provides typical timing representation of various PLB transfers initiated
by the PLBV46 Master. The User must realize that actual timing relationships will vary due to
arbitration timing, dynamic PLB Slave response characteristics, and values assigned by the User for the
Master’s parameters.
The provided timing diagrams are indicative of a Master that is attached to a 64-bit PLB and has a
matching native data width of 64 bits. The LocalLink Backends have been configured to be
asynchronous to the PLB Clock and therefore the Client IP must provide the Read and Write LocalLink
synchronization clocks. Operating in this mode also contributes to additional latency in the transaction
timing of Client IP requests.
The threshold parameter C_RDFIFO_LLTRANS_THRES also can change transaction behavior for read
operations. The User needs to review the parameter’s definition in Table 2, “PLBV46 Master Design
Parameters,” on page 22 and in the detailed parameter description section see "PLB Master Parameter
Detailed Descriptions" on page 25.
DS566 April 24, 2009
www.xilinx.com
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Product Specification