DS566 Datasheet, PDF (5/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
good example of this is if the Read FIFO is approaching a full condition, the Read Controller may not
be able to post a burst read request on the PLB because the incoming read data would overrun the Read
FIFO.
If asynchronous Read LocalLink operation has been specified (see parameter
C_RD_LLINK_IS_ASYNC), the Read LocalLink interface to the IP Client is synchronized to an input
clock (IP2Bus_MstRd_clk) that is provided by the IP Client. If synchronous Read LocalLink interface
operation has been specified, the Read LocalLink interface utilizes the PLB Bus clock for the timing
standard and the IP2Bus_MstRd_clk is ignored by the Master. On the write side of the Read FIFO,
operations are coordinated by the Read Controller which is always synchronous to the PLB clock.
Write Controller
The Write Controller provides the IP Client with the capability to perform PLB write transactions in the
form of Singles and Fixed Length Bursts. The IP Client initiates a write transaction via the Write
Controller’s Command interface. The Write Command interface is separate from the Read Command
interface bus has the same signal set. This is graphically shown in Figure 3. The interface is a a mix of
request, qualifier, and status reply signals and buses. These signals are detailed in Table 1, “PLBV46
Master I/O Signal Description,” on page 9.
Like the Read Controller, the Write Controller orchestrates the initiation of write requests to the Master
Request Controller and the associated write data transfer to the PLB from the Write LocalLink Backend.
A Client IP may request a large burst write transfer of hundreds or thousands of bytes. The Write
Controller must examine the start and end conditions of the burst request to determine if a single data
beat write is required to start and end the request and breaks up the intermediate burst operations into
fixed length burst write requests of 2 to 16 data beats. At the same time, the Write Controller must
monitor the Write LocalLink Backend status and adjust it’s PLB Write request generation as the status
changes due to rate at which the Client IP is providing the Write Data. All operations and interfaces on
the Read Controller are synchronous with the PLB clock.
Write LocalLink Backend
Write data transfer from the IP Client is handled by the Write LocalLink Backend. The module utilizes
the Xilinx LocalLink transfer protocol. The module incorporates either an asynchronous Core
Generator system FIFO or a synchronous Core Generator system FIFO for the WrFIFO. The Write FIFO
is used as a time domain transform mechanism and as an intermediate storage device. Data is written
into the WrFIFO by the Write LocalLink Controller.
If asynchronous Write LocalLink operation has been specified (see parameter
C_WR_LLINK_IS_ASYNC), the Write LocalLink to WrFIFO operations are synchronized to an input
clock (IP2Bus_MstWr_clk) that is provided by the IP Client. If synchronous Write LocalLink interface
operation has been specified, the Write LocalLink interface utilizes the PLB Bus clock for the timing
standard and the IP2Bus_MstWr_clk is ignored. On the read side of the Write FIFO, operations are
coordinated by the Write Controller which is always synchronous to the PLB clock.
Read and Write Command Interfaces
The Read and Write Controllers within the PLBV46 Master serve the IP Client via a command interface.
The basic command interface is symmetrical between Read and Write Controllers. The command
interface is how the Client IP makes request for data transfer to the Master and how the Master Service
provides high level status of the transfer back to the IP Client, The basic command interface consists of
the following:
DS566 April 24, 2009
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Product Specification