DS566 Datasheet, PDF (3/38 Pages) Xilinx, Inc – PLBV46 Master

.
Figure Top x-ref 1
PLBV46 Master (v1.00a)
Read Dataphase Control/Reply
Read Data Bus
PLBV46 Master V1_00_a
Read Command Status
Read Controller
(32/64/128-bit)
Grant Req
Read Command Request & Qualifiers
LocalLink Status
Read Data
Read
LocalLink
Backend
Read LocalLink
(32/64/128-bit)
Address Phase Request/Qualifiers
Address Phase Reply
CC & BLE
Adapter
Request
Cont^tr^eo^xt ller
Client IP
Interface
W rite Dataphase Control/Reply
Write Data Bus
Grant Req
Write Command Status
Write Command Request & Qualifiers
Write Controller
(32/64/128-bit)
LocalLink Status
W rite Data
Write
LocalLink
Backend
Write LocalLink
(32/64/128-bit)
Figure 1: PLBV46 Master Block Diagram
DS566_01_033009
Request Controller
The Request Controller is designed to manage the Address Phase of PLB requests. The Address Phase
is defined as the time from the assertion of M_request by the Master to either the receipt of
PLB_addrAck from the PLB. A transaction request is initiated by the IP Client via the Write Controller
or the Read Controller. As part of its responsibility, the Request Controller must arbitrate between the
Read and Write Controllers when requests are being posted simultaneously. The Read and Write
Controllers are provided with a Grant signal when it is being given access to the PLB by the Request
Controller.
The Request Controller Arbiter monitors requests from the Read and the Write Controllers. When
simultaneous requests occur and arbitration is required, the Arbiter is designed to give priority to Write
requests over Reads. However, the Arbiter is designed such that access starvation cannot occur. At the
completion of a request arbitration cycle, a pending request from a different Controller is given priority
over the Controller that has already been given a grant and is completing it’s resulting data phase.
DS566 April 24, 2009
www.xilinx.com
3
Product Specification