DS566 Datasheet, PDF (16/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
Table 1: PLBV46 Master I/O Signal Description
Signal Name
Interface Signal Type Init Status
Description
IP2Bus_MstRd_Vacancy(0:C_RDF
IFO_VACANCY_WIDTH-1)
IP Read
LocalLink
Intfc.
Input
This field is only used by
the Read Controller when
the Read FIFO has been
omitted from the Read
LocalLink Backend and
the parameter
C_RDFIFO_VACANCY_
WIDTH is 2 or greater.
This bus is driven by the
User IP and indicates the
available space in a User
IP FIFO that the Read
Controller will be writing
data to via the Write
LocalLink. The Read
Controller will stop posting
Read requests to the PLB
if the value of this bus
drops below a
parameterized threshold.
If the User IP does not
implement a FIFO, then
the bus should be driven
with all bits asserted
indicating maximum
space available at all
times or assign the
C_RDFIFO_VACANCY_
WIDTH parameter to a
value of 1.
IP Client Write Command I/O Signals
IP2Bus_MstWr_Req
IP Write
Command
Intfc.
Input
Active high signal initiating
a Write transaction. This
signal and associated
qualifiers must be
asserted and held until the
Bus2IP_MstWr_CmdAck
reply signal is sampled as
asserted. At that time, the
IP2Bus_MstWr_Req must
be deasserted.
IP2Bus_MstWr_Addr(0 :
C_PLB_AWIDTH-1)
IP Write
Command
Intfc.
Input
Address bus from the
User IP used to convey
the desired starting
address to be output on
the PLB Bus during the
requested IP Write
operation.
The qualifier must be
stable and valid during the
assertion of the
IP2Bus_MstWr_Req
signal.
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DS566 April 24, 2009
Product Specification