DS566 Datasheet, PDF (27/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
a range of 1 to log2(C_RDFIFO_DEPTH)+1. The Bus2IP_MstRd_RdCnt bus is populated from the
most significant bit towards the least significant bit.
Notes:
1. For asynchronous Read FIFOs, this value is set to log₂(C_RDFIFO_DEPTH+1). The Master design
incorporates additional logic on the Read side of the LocalLink Async FIFOs such that one extra data value is
available. Thus the reported read count value can indicate a value that is one more than expected based on the
parameterized depth of the FIFO. (I.E. An async FIFO of depth 511 can have a read count value of 512 when
the FIFO is filled to capacity and kept full by the writing logic.
2. For synchronous Read FIFOs (Core Generator tool and SRL), this value is set to log₂(C_RDFIFO_DEPTH)+1.
C_RDFIFO_VACANCY_WIDTH
This parameter is reserved and should be set to 1.
C_RDFIFO_LLTRANS_THRES
This integer parameter specifies the minimum number of stored entries (occupancy) that must be
present in the RdFIFO before the Read LocalLink will initiate a data transfer (asserting the
Bus2IP_MstRd_src_rdy_n) on the Read LocalLink interface. The value entered for this parameter must
be established by the User to minimize excessive throttling (due to the RdFIFO going Empty) by this
Master when the Read Controller is loading data into the RdFIFO at a slower rate than the User IP is
accepting it. This can occur if the User IP IP2Bus_MstRd_clk frequency is higher than the PLB clock or
the PLB Slave providing the read data is throttling the PLB transfer. This threshold is overridden when
the Read Controller loads the RdFIFO with an EOP flag (EOP indicates the last data word of a
requested data transfer).
Note:
1. This parameter value must not exceed the value of C_RDFIFO_DEPTH-16 when C_RDFIFO_DEPTH is 16 or
greater.
2. The use of Fixed Length Burst transfers that may start on an unaligned address boundary require this value to
be set to no less than C_RDFIFO_DEPTH-17 to account for the starting Single data beat (to align to a Master
Native Dwidth boundary) and an initial Fixed Length Burst of up to 16 data beats. This condition will require the
RdFIFO depth to be set to at least 32 storage locations.
C_REM_WIDTH
This integer parameter specifies the size of the Bus2IP_MstRd_rem and Bus2IP_MstWr_rem bus bit
widths. If the rem is not going to be used, then the parameter is assigned a value of 1. If rem is going to
be used (the normal case), then the value assigned to this parameter must be derived from the value
assigned to C_MPLB_NATIVE_DWIDTH. For an encoded representation, the assigned value must be
log₂(C_MPLB_NATIVE_DWIDTH/8). For a Mask representation, the value assigned must be
C_MPLB_NATIVE_DWIDTH/8.
Note: The LocalLink rem value is stored in the Read and Write FIFOs with the data values so FIFO
memory resources may fluctuate depending on this parameter’s assigned value.
C_REM_CODING
This integer parameter specifies the coding representation of the values placed on the
Bus2IP_MstRd_rem and Bus2IP_MstWr_rem buses during data transmission. Either encoded
representation (=1) or mask representation (=2) may be selected. The use of Encoded format has use
restrictions in that single data beat transfers cannot always be accurately represented. In these cases, the
User needs to drive the REM value to "all bytes valid" and use a Single Data Beat command with the
desired Byte Enables set. Mask representation is the recommended use format.
DS566 April 24, 2009
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Product Specification