DS566 Datasheet, PDF (11/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
Table 1: PLBV46 Master I/O Signal Description
Signal Name
Interface Signal Type Init Status
Description
IP2Bus_MstRd_Addr(0 :
C_MPLB_AWIDTH-1)
IP Read
Command
Intfc.
Input
Address bus from the
User IP used to convey
the desired starting
address to be output on
the PLB Bus during the
requested IP Write
operation.
The qualifier must be
stable and valid during the
assertion of the
IP2Bus_MstRd_Req
signal.
IP2Bus_MstRd_Length(0 :
C_LENGTH_WIDTH-1)
IP Read
Command
Intfc.
Input
This command qualifier
bus specifies the
not-to-exceed number of
bytes to be transferred for
the read command.
The qualifier must be
stable and valid during the
assertion of the
IP2Bus_MstRd_Req
signal.
IP2Bus_MstRd_BE(0 :
(C_MPLB_NATIVE_DWIDTH/8)
-1)
IP Read
Command
Intfc.
Input
Byte Enable bus from the
User IP used to convey
the desired Byte Enables
output on the PLB Bus
during a Single Data Beat
read operation. This
qualifier is only valid
during Single Data Beat
requests.
The qualifier must be
stable and valid during the
assertion of the
IP2Bus_MstRd_Req
signal.
DS566 April 24, 2009
www.xilinx.com
11
Product Specification