DS566 Datasheet, PDF (22/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
Design Parameters
The PLBV46 Master has interface features and functional features that are parameterizable via VHDL
Generic assignments. The names and description of thee parameters are shown in Table 2.
Table 2: PLBV46 Master Design Parameters
Feature/Description
Parameter Name
Allowable Values
Default
Values
VHDL
Type
IP Command Interface
This parameter sets the
needed bit width of the
IP2Bus_MstRd_Length and
IP2Bus_MstWr_Length input
ports.
C_LENGTH_WIDTH
8 to 30
12
Integer
PLB Master Request Interface
0 to 4
This parameter sets the initial
priority for any request issued C_START_PRIORITY
by this PLB Master.
0,1,2, 3 = starting PLB
request priority
4
4 = Priority fixed at 0
Integer
This parameter specifies a
time-out interval (in number
0 to 127
of PLB clocks) that, when
expired, will cause this
Master to bump (increase)
the request priority value
C_PRIORITY_BUMP_TI
MEOUT
0 = Priority Bumping
logic omitted
1-127 = number of PLB
0
(during an active request).
clocks set for bumping
The actual time interval will
interval (plus 2 clocks
be 2 greater than the value
for internal registering)
assigned to this parameter.
Integer
Write LocalLink FIFO Properties
0 = Write LocalLink
Interface is
This Parameter specifies the
synchronous to PLB
Write LocalLink interface
clocking relationship to the
C_WR_LLINK_IS_ASYN Clock
C
1 = Write LocalLink
0
PLB Bus Clock
Interface is
asynchronous to PLB
Clock
Integer
This Parameter specifies the
use of SRL16 based memory
core for the Write FIFO if the
Write LocalLink backend is
synchronous to the Bus
Clock.
C_USE_SRL_WRFIFO
0 = Write FIFO will use
BRAM memory core
1 = Write FIFO will use
SRL16 based memory
core
0
Integer
This parameter sets the
depth of the Write FIFO
C_WRFIFO_DEPTH
16 to 16,384
(must be 2^N-1 for
Async fifo; must be 2^N
512
for Sync FIFO; must be
16, 32, or 64 for SRL
fifo).
integer
22
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DS566 April 24, 2009
Product Specification