DS566 Datasheet, PDF (36/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
Design Implementation
Target Technology
The target technology is an FPGA listed in EDK Supported Device Families.
Device Utilization and Performance Benchmarks
Since the PLB Master is a module that will be used with other design modules in the FPGA, the
utilization and timing numbers reported in this section are just estimates. As the PLB Master is
combined with other pieces of the FPGA design, the utilization of FPGA resources and timing will vary
from the results reported here.
Three different groups of parameter settings have been chosen to represent a Full-up 128-bit, a Typical
64-bit, and a 32-bit (using SRL FIFOs) implementation of the PLBV46 Master. These settings are
indicated in Table 6.
In order to analyze the PLB Master timing within an FPGA, a design wrapper was created that
instantiated the PLB Master with registers on all of the module’s inputs and outputs. This allowed a
constraint to be placed on the clock nets for the design to yield more realistic timing results. The Xilinx
ISE Synthesis tool (XST) was run on the wrapper and the synthesis results used for the information
presented here. Some selected configurations of the PLBV46 Master were implemented and the
resulting FPGA performance and resource utilization benchmarks are shown in Table 5..
Table 5: Performance and Resource Utilization Benchmarks for the Virtex®-5 FPGA
Parameter Settings Group
Device Resources
F_MAX
(MHz)
Slices
Slice Flip-
Flops
4-input
LUTs
BRAMs
F_MAX
Full-up 128-bit with
Async BRAM based FIFOs
16K deep
2166
1940
130 (36k)
3438
or
125
260 (18K)
Typical 64-bit with
Sync BRAM based FIFOs
512 deep
3 (36K)
855
849
1265
or
130
6 (18K)
32-bit with
SRL FIFOs,
32 deep
512
502
986
0
140
Table 6: Parameter Settings for Resource Utilization Estimates
Parameter Name
Full-up 128-bit Typical 64-bit
C_LENGTH_WIDTH
C_START_PRIORITY
C_PRIORITY_BUMP_TIMEOUT
30
16
1
1
64
16
32-bit SRL
FIFO
12
4
0
36
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DS566 April 24, 2009
Product Specification