DS566 Datasheet, PDF (8/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
Xilinx LocalLink Interface Summary
The Client IP receives data from and transmits data to the PLB Master via the Xilinx LocalLink Interface
protocol. LocalLink is a point-to-point, synchronous interface intended for high data rate applications.
Because data flow is unidirectional, the PLB Master employs two LocalLink interfaces, one for IP Client
data read operations and one for IP Client data write operations. The Read and Write interfaces are
independent from each other and thus enable the PLB Master to support simultaneous Read and Write
data transfers with the IP Client. This enables the PLB Master to leverage the split bus architecture of
the PLB and eliminates any need for PLB IPIF support logic to decode addresses and mechanize the
data transfers.
LocalLink is based upon the concept of a Source device transmitting data to a Destination device. Data
flow is unidirectional; always from the Source to the Destination. Both Source and Destination can
throttle transfers as well as choose to discontinue the transfer. In order for a transfer data beat to
complete., both the Source and the Destination must signal that they are ready at the rising edge of the
transfer synchronization clock (clk). The Source indicates a ready condition by asserting the src_rdy_n
signal. The Destination indicates ready by asserting the dst_rdy_n signal.
Data (d[n:0]) is transferred in a delimited group otherwise known as a packet. The start of a packet is
delimited with the assertion of the Start-of-Frame signal (sof_n) by the Source. The assertion of
End-of-Frame by the Source (eof_n) delimits the last data beat of a packet. A single data beat transfer is
delimited with simultaneous assertion of sof_n and eof_n.
Transfer acknowledge/throttling is accomplished with the assertion of src_rdy_n and dst_rdy_n.
De-assertion of either signal will throttle the transfer. If the Destination device can no longer transfer
data or no longer needs data, it may assert the dst_dsc_n to discontinue the transfer. Conversely, the
Source may terminate transmission prematurely with the assertion of the src_dsc_n signal.
The rem[0:n] signal (short for remainder) is set by the Source during each data beat in which a delimiter
flag is set (sof_n, sop_n, eop_n, eof_n). The value asserted specifies the valid bytes in that data beat and
are somewhat application specific depending on the needs of the source and destination devices. The
rem can be either an encoded value or a masked value and is set via parameterization. The active
assertion level is parameterizable active high or active low depending on the User needs. Byte lane
ordering follows PLB byte lane ordering (0 is MSB).
A basic LocalLink data transfers are shown in Figure 4. The data packet consists of 16 data beats of 64
bits wide. The diagram shows both the Source and Destination throttling the transfer.
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DS566 April 24, 2009
Product Specification