DS566 Datasheet, PDF (25/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
PLB Master Parameter Detailed Descriptions
C_LENGTH_WIDTH
This is an integer parameter has a range of 8 to 30 and specifies the width (in bits) of the
IP2Bus_MstRd_Length and IP2Bus_MstWr_Length input port. The number of bits will limit the
maximum read or write length (in bytes) that can be specified via the read and write command
interfaces. For example, the default value of 12 will limit the requested read or write length to 4096
bytes.
C_START_PRIORITY
This integer parameter has a range of 0 to 4. It specifies to the Master what the initial assertion of the
M_priority output bus will be for any request posted by this Master. The M_priority bus is used by the
PLB Arbiter during request arbitration of the PLB. The higher priority request is granted access ahead
of lower priority requests. A value of 0 is lowest priority and a value of 3 is highest priority. A value of
4 will fix the priority at 0 and priority bumping will be disabled. If enabled, the priority bumping logic
which will increase request priority from this starting value at predefined time intervals (see
C_PRIORITY_BUMP_TIMEOUT) until highest priority (3) is reached or the Master request is
acknowledged.
C_PRIORITY_BUMP_TIMEOUT
This integer parameter has a range of 0 to 127 and specifies a priority bumping time-out period (in PLB
clocks) that is allowed to elapse during a request assertion by this Master. If the time-out expires, the
Master will increment the asserted request priority (via M_priority) to the next priority level and
reinitialize the priority bumping timeout counter. This sequence continues until the request is
acknowledged, the request is aborted, or highest priority is reached. If a value of 0 is assigned to this
parameter, the priority bumping logic is removed. Request priority will be fixed to that specified by the
C_START_PRIORITY parameter.
Note that there is an additional 2 clocks of timeout realized due to internal registering and counter
management.
C_WR_LLINK_IS_ASYNC
This integer parameter specifies the needed clocking relationship of the Write LocalLink interface and
the PLB Bus clock. When set to 1, the Write LocalLink Interface must be supplied with a User clock and
an Asynchronous Core Generator system FIFO will be instantiated for the Write FIFO. If set to 0, the
Write LocalLink Interface will use the PLB Bus clock and a Synchronous Core Generator system FIFO
or SRL based FIFO will be instantiated for the Write FIFO. Note that asynchronous operation induces
more latency in initiating and completing write transfers.
C_USE_SRL_WRFIFO
If the Write LocalLink interface is synchronous to the PLB Clock (see C_WR_LLINK_IS_ASYNC), then
this parameter allows the User to select the use of an SRL16 based implementation of the Write FIFO.
This will eliminate the use of BRAMs for the FIFO. If selected, the C_WRFIFO_DEPTH can be 16, 32, or
64.
C_WRFIFO_DEPTH
This integer parameter applies to the Write Controllers. This integer parameter specifies the storage
depth of the WrFIFO. The width of the WrFIFO is automatically set to the value of
C_MPLB_NATIVE_DWIDTH plus LocalLink packet delimiters (2) and LocalLink REM (0 to 16 bits
DS566 April 24, 2009
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Product Specification