DS566 Datasheet, PDF (10/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
Table 1: PLBV46 Master I/O Signal Description
Signal Name
Interface Signal Type Init Status
Description
M_abort
PLB Bus
Output
’0’
See table note 1.
M_UABus(0 : 31)
PLB Bus
Output
all ’0’
See table note 1.
M_ABus(0 : 31)
PLB Bus
Output
all ’0’
See table note 1.
M_wrDBus(0 :
C_MPLB_DWIDTH-1)
PLB Bus
Output
all ’0’
See table note 1.
M_wrBurst
PLB Bus
Output
’0’
See table note 1.
M_rdBurst
PLB Bus
Output
’0’
See table note 1.
PLB Request Reply Signals
PLB_MAddrAck
PLB Bus
Input
See table note 1
PLB_MSSize(0 : 1)
PLB Bus
Input
See table note 1
PLB_MRearbitrate
PLB Bus
Input
See table note 1
PLB_MTimeout
PLB Bus
Input
See table note 1
PLB_MBusy
PLB Bus
Input
See table note 1
PLB_MRdErr
PLB Bus
Input
See table note 1
PLB_MWrErr
PLB Bus
Input
See table note 1
PLB_MIRQ
PLB Bus
Input
See table note 1
PLB_MRdDBus(0 :
C_MPLB_DWIDTH-1)
PLB Bus
Input
See table note 1
PLB_MRdWdAddr(0 : 3)
PLB Bus
Input
See table note 1
PLB_MRdDAck
PLB Bus
Input
See table note 1
PLB_MRdBTerm
PLB Bus
Input
See table note 1
PLB_MWrDAck
PLB Bus
Input
See table note 1
PLB_MWrBTerm
PLB Bus
Input
See table note 1
IP Client Read Command I/O Signals
IP2Bus_MstRd_Req
IP Read
Command
Intfc.
Input
Active high signal initiating
a Write transaction. This
signal and associated
qualifiers must be
asserted and held until the
Bus2IP_MstRd_CmdAck
reply signal is sampled as
asserted. At that time, the
IP2Bus_MstRd_Req must
be deasserted.
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DS566 April 24, 2009
Product Specification