DS566 Datasheet, PDF (12/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
Table 1: PLBV46 Master I/O Signal Description
Signal Name
Interface Signal Type Init Status
Description
IP2Bus_MstRd_Size(0 : 1)
IP Read
Command
Intfc.
Input
Read Command qualifier
bus used to indicate the
transfer width for a Fixed
Length Burst transfer on
the PLB. This qualifier is
only valid during Burst
requests.
00 = Words (32 bits)
01 = Double Words (64
bits)
10 = Quad words
11 = Reserved
The qualifier must be
stable and valid during the
assertion of the
IP2Bus_MstRd_Req
signal.
IP2Bus_MstRd_Type
IP Read
Command
Intfc.
Input
Read Command qualifier
bus used to indicate the
desired transfer type to be
requested by the Master.
’0’ = Single Data Beat
’1’ = Fixed Length Burst
The qualifier must be
stable and valid during the
assertion of the
IP2Bus_MstRd_Req
signal.
IP2Bus_MstRd_Lock
IP Read
Command
Intfc.
Input
Reserved:
Drive input to logic ’0’.
Read Bus Lock not
currently supported.
IP2Bus_MstRd_Reset
IP Read
Command
Intfc.
Input
Active high signal
’0’
requesting a
reinitialization of the Write
logic and Read FIFO.
Bus2IP_MstRd_CmdAck
IP Read
Command
Intfc.
Output
Active high signal
asserted for one PLB
Clock period to indicate
that the PLB Bus has
accepted the Read
’0’
Command request and
the data phase is being
initiated. Request and
qualifiers must be
deasserted when this
signal is sampled as
asserted.
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DS566 April 24, 2009
Product Specification