DS566 Datasheet, PDF (34/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
Fixed Length Burst Read Operation
Figure Top x-ref 7
0ns
MPLB_Clk
200ns
400ns
600ns
800ns
1.0us
1.2us
M_request
M_abort
M_buslock
M_priority[0:1]
M_ABus[0:31]
M_RNW
M_BE[0:7]
M_MSize[0:1]
M_size[0:3]
M_type[0:2]
M_wrDBus[0:63]
M_wrBurst
M_rdBurst
1
10000000
F0
01
B
0
PLB_MaddrAck
PLB_MSsize[0:1]
PLB_MRearbitrate
PLB_MBusy
PLB_MRdErr
PLB_MWrErr
PLB_MrdBterm
PLB_MrdDAck
PLB_MrdDbus[0:63]
PLB_MwrBterm
PLB_MWrDAck
1
0 1 2 3 4 5 6 7 8 9 1011 12131415
IP2Bus_MstRd_Req
IP2Bus_MstRd_Addr[0:31]
IP2Bus_MstRd_Length[0:11]
IP2Bus_MstRd_BE[0:7]
IP2Bus_MstRd_Size[0:1]
IP2Bus_MstRd_Type
IP2Bus_MstRd_Lock
IP2Bus_MstRd_Reset
10000000
080
XX
01
Bus2IP_MstRd_CmdAck
Bus2IP_MstRd_Cmplt
Bus2IP_MstRd_Error
Bus2IP_MstRd_Rearbitrate
Bus2IP_MstRd_Cmd_Timeout
Bus2IP_MstRd_Length_is_Zero
IP2Bus_MstRd_Clk
Bus2IP_MstRd_src_rdy_n
Bus2IP_MstRd_src_dsc_n
Bus2IP_MstRd_sof_n
Bus2IP_MstRd_sop_n
Bus2IP_MstRd_eop_n
Bus2IP_MstRd_eof_n
Bus2IP_MstRd_d[0:63]
Bus2IP_MstRd_rem[0:7]
IP2Bus_MstRd_dst_rdy_n
IP2Bus_MstRd_dst_dsc_n
Bus2IP_MstRd_RdCnt[0:8]
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
FF
FF
000
012 002 003 005 007 010
013 000 010 009 008 007 006 005 004 003 002 001
C_RDFIFO_LLTRANS_THRES set to 4.
DS566_07_033009
Figure 7: PLBV46 Master Fixed Length Burst Read Timing
34
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DS566 April 24, 2009
Product Specification