DS566 Datasheet, PDF (17/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
Table 1: PLBV46 Master I/O Signal Description
Signal Name
Interface Signal Type Init Status
Description
IP2Bus_MstWr_Length(0 :
C_LENGTH_WIDTH-1)
IP Write
Command
Intfc.
Input
This command qualifier
bus specifies the
not-to-exceed number of
bytes to be transferred for
a write command. The
qualifier must be stable
and valid during the
assertion of the
IP2Bus_MstWr_Req
signal.
IP2Bus_MstWr_BE(0 :
(C_MPLB_NATIVE_DWIDTH/8)
-1)
IP Write
Command
Intfc.
Input
Byte Enable bus from the
User IP used to convey
the desired Byte Enables
to be output on the PLB
Bus during IP Single Data
Beat Write operations.
The qualifier must be
stable and valid during the
assertion of the
IP2Bus_MstWr_Req
signal.
IP2Bus_MstWr_Size(0 : 1)
IP Write
Command
Intfc.
Input
Write Command qualifier
bus used to indicate the
transfer width for a Fixed
Length Burst transfer on
the PLB. This qualifier is
only valid during Burst
requests.
00 = Words (32 bits)
01 = Double Words (64
bits)
10 = Quad words
11 = Reserved
The qualifier must be
stable and valid during the
assertion of the
IP2Bus_MstWr_Req
signal.
IP2Bus_MstWr_Type
IP Write
Command
Intfc.
Input
Write Command qualifier
bus used to indicate the
desired transfer type to be
requested by the Master.
’0’ = Single Data Beat
’1’ = Fixed Length Burst
The qualifier must be
stable and valid during the
assertion of the
IP2Bus_MstWr_Req
signal.
DS566 April 24, 2009
www.xilinx.com
17
Product Specification