DS566 Datasheet, PDF (4/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
A special arbitration modification is used in the case of PLB rearbitration of a Master’s request. If a
Read request is rearbitrated, then the Arbiter checks for a pending Write from the Write Controller. If a
Write is pending, the Arbiter will grant PLB access to the pending Write. However, if a Write Request is
rearbitrated, the Arbiter will ignore any pending Read request and continue to grant the Write access to
the PLB. This scheme is required for PCIE Bridge applications.
Conversion Cycle and Burst Length Expansion Adapter (CC & BLE Adapter)
The CC/BLE Adapter adds the ability for the Master to support Conversion Cycles and Burst Length
Expansion. These functions are required if the Master accesses a PLB Slave that has a Native Data
Width that is smaller than the Native Data Width of the Master. The CC/BLE Adapter is automatically
included or omitted from the Master implementation depending on the assigned values for the
C_MPLB_NATIVE_DWIDTH and C_MPLB_SMALLEST_SLAVE. If C_MPLB_SMALLEST_SLAVE is
smaller than C_MPLB_NATIVE_DWIDTH, then the CC/BLE Adapter will be included automatically.
However, if a User knows that the Master will never be accessing any Slave that is narrower than the
Master’s Native Data Width, then the adapter can be omitted manually by assigning the parameter
C_INHIBIT_CC_BLE_INCLUSION a value of 1.
Read Controller
The Read Controller provides the IP Client with the capability to perform PLB read transactions in the
form of Singles and Fixed Length Bursts. The IP Client initiates a read transaction via the Read
Controller’s Command interface. The Read Command signal set is graphically shown in Figure 2. The
interface is a a mix of request, qualifier, and status reply signals and buses. These signals are detailed in
Table 1, “PLBV46 Master I/O Signal Description,” on page 9.
The Read Controller orchestrates the initiation of requests to the Master Request Controller and the
associated read data transfer from the PLB to the Read LocalLink Backend. A Client IP may request a
large burst read transfer of hundreds or thousands of bytes. The Read Controller must examine the
start and end conditions of the burst request to determine if a single data beat is required to start and
end the request and breaks up the intermediate burst operations into fixed length burst requests of 2 to
16 data beats. At the same time the Read Controller must monitor the Read LocalLink Backend status
and adjust it’s PLB Read request generation as that status changes due to rate at which the Client IP is
consuming the Read Data. All operations and interfaces on the Read Controller are synchronous with
the PLB clock.
Read LocalLink Backend
Read data transfer from the Master to the IP Client is handled by the Read LocalLink Backend. It
utilizes the Xilinx LocalLink transfer protocol. The LocalLink protocol has been developed to support
high data rate transmissions required by networking type IP. It dovetails well with the use of FIFOs as
an intermediate data storage element. This protocol is documented in the Xilinx document SP006 titled
LocalLink Interface Specification. These signals are also detailed in Table 1, “PLBV46 Master I/O Signal
Description,” on page 9.
Via parameterization, the module can be customized to incorporate an asynchronous Core Generator
FIFO, a synchronous Core Generator system FIFO, or an SRL based FIFO. This FIFO is referred to as the
Read FIFO. The Read FIFO may be used as a time domain transform mechanism and as an intermediate
storage device. Data is written into the RdFIFO by the Read Controller synchronous to the PLB clock.
The Read LocalLink Backend provides status information to the Read Controller so that the Read
Controller can adapt it’s PLB Read request generation to the state of the Read LocalLink Backend. A
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DS566 April 24, 2009
Product Specification