DS566 Datasheet, PDF (20/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
Table 1: PLBV46 Master I/O Signal Description
Signal Name
Interface Signal Type Init Status
Description
IP2Bus_MstWr_rem(0 :
C_REM_WIDTH-1)
IP Write
LocalLink
Intfc.
Input
One, Three, or eight bit
bus indicating the valid
Bytes in the associated
LocalLink data bus
(Bus2IP_MstRd_d). It is
sampled when any of the
LocalLink delimiter signals
are asserted.
IP2Bus_MstWr_d(0 :
C_MPLB_NATIVE_DWIDTH-1)
IP Write
LocalLink
Intfc.
Input
Write Data bus. A data
packet is started with the
assertion of the
Bus2IP_MstWr_sof_n and
ended with the assertion
of the
Bus2IP_MstWr_eof_n.
IP2Bus_MstWr_src_rdy_n
IP Write
LocalLink
Intfc.
Input
Active low signal
indicating the Primary
LocalLink Write interface
is able to accept data from
IP client. A data transfer
occurs when both the
Bus2IP_MstWr_dst_rdy_
n and the
IP2Bus_MstWr_src_rdy_
n are asserted on the
rising edge of the Write
LocalLink synchronization
clock.
IP2Bus_MstWr_src_dsc_n
IP Write
LocalLink
Intfc.
Input
Active low signal
indicating to the Write
interface that the IP Client
is discontinuing the
transfer.
Bus2IP_MstWr_dst_rdy_n
IP Write
LocalLink
Intfc.
Output
Active low signal
indicating to the IP Client
that the Write interface is
ready to accept data. A
data transfer occurs when
both the
’1’
Bus2IP_MstWr_dst_rdy_
n and the
IP2Bus_MstWr_src_rdy_
n are asserted on the
rising edge of the Write
LocalLink synchronization
clock.
Bus2IP_MstWr_dst_dsc_n
IP Write
LocalLink
Intfc.
Output
Active low signal
’1’
indicating to the IP Client
that the Write interface is
discontinuing the transfer.
20
www.xilinx.com
DS566 April 24, 2009
Product Specification