DS566 Datasheet, PDF (21/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
Table 1: PLBV46 Master I/O Signal Description
Signal Name
Interface Signal Type Init Status
Description
Bus2IP_MstWr_WrCnt(0 :
C_WRFIFO_WRCNT_WIDTH-1)
IP Write
LocalLink
Intfc.
Output
All ’0’
This bus reflects the
number of words that are
loaded in the Write FIFO.
It is synchronous to the
Write LocalLink
synchronization clock.
This bus may be used by
the User IP to monitor the
occupancy of the WrFIFO.
IP2Bus_MstWr_Occupancy(0:C_
WRFIFO_OCCUPANCY_WIDTH-
1)
IP Write
LocalLink
Intfc.
Input
This field is only used by
the Write Controller when
the Write FIFO has been
omitted from the Write
Controller and the
parameter
C_WRFIFO_OCCUPANC
Y_WIDTH is 2 or greater.
This bus is driven by the
User IP and indicates the
available data in a User IP
FIFO that the Write
Controller will be receiving
via the Write LocalLink.
The Write Controller will
stop posting Write
requests to the PLB if the
value of this bus drops
below a parameterized
threshold. If the User IP
does not implement a
FIFO, then the bus should
be driven with all bits
asserted indicating
maximum data available
at all times or assign the
C_WRFIFO_OCCUPANC
Y_WIDTH parameter to a
value of 1.
Notes:
1. This signal’s function and timing is defined in the IBM_® 128-Bit Processor Local Bus Architecture
Specification Version 4.6.
2. The LocalLink REM bus has parameterizable assertion polarity. The init state of the REM bus that is output by
the Master is the opposite of the active assertion state.
DS566 April 24, 2009
www.xilinx.com
21
Product Specification