DS566 Datasheet, PDF (30/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
Register Descriptions
This Master does not incorporate any programmable or User accessible registers.
User Application Topics
Native Data Width and PLB Data Width
The PLBV46 Master has parameters (C_MPLB_DWIDTH) that allow the core to be configured for
connection to three different PLB data bus widths (32, 64, and 128 bits). In addition, another parameter
(C_MPLB_NATIVE_DWIDTH) allows the Master to be configured to one of three different internal
data widths (32, 64, and 128 bits). The internal data width is also defined as the native data width. The
native data width selection cannot exceed the PLB data bus width or alternatively, the PLB data bus
width cannot be less than the assigned Native data width value of the Master. The native data width is
also the width of the LocalLink interfaces with the IP Client.
In the case that the PLB data bus width is wider than the native data width, the Master incorporates
mirroring logic to mirror the write data bus per the PLB requirements. This eliminates the need for this
logic in the PLB Bus structure. Also per the PLB requirements, the Master will only use the appropriate
slice of the Read Data bus that matches it’s native data width. The remaining portion of the PLB Read
Data bus is ignored.
Unaligned Read Transfers
The PLBV46 Master supports unaligned burst read transfer requests. An unaligned request is defined
as having a starting address that is not aligned to a multiple of the Master’s native data bus width
and/or the specified Length qualifier causes a burst end condition where the last data beat is not a full
native data bus width. Under these conditions, the Read Controller will detect unaligned start and end
conditions of a burst and adapt automatically. An unaligned start condition will cause the Master to
calculate and submit a single data beat PLB read request for the unaligned starting data bytes. The Read
Controller then calculates and requests burst transfers using the full data bus width until completed. If
an unaligned end condition is detected, the Read Controller will initiate PLB Burst transfers of the full
data bus width until the last data beat. For the last data beat, the Read Controller will calculate and
submit a single data beat PLB read request for the remaining unaligned starting data bytes. Thus, a
general unaligned burst transfer request may be required to be mechanized on the PLB by the Read
Controller as a starting single beat, a series of bus-width bursts, and then ending with a single data beat
Short burst requests are also automatically converted. For example, a read request for Fixed Length
burst type may be requested via the Read Command interface and the associated Length and starting
address values may be such that the transfer cannot be performed with a burst transfer request on the
PLB. The Read Controller will automatically convert to single data beat requests on the PLB to
complete the transfer.
Unaligned Write Transfers
The PLBV46 Master also supports unaligned burst write transfer requests. As with the Read side,
unaligned write request is defined as having a resolved starting address that is not aligned to a multiple
of the Master’s native data bus width and/or the specified Length qualifier causes a burst end
condition where the last data beat is not a full data bus width. The Write Controller side also has one
additional unaligned transfer condition that is determined by the actual LocalLink REM values
received from the User IP via the Write LocalLink interface. Under these conditions, the Write
Controller Service will detect unaligned start and end conditions of a burst and adapt automatically.
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DS566 April 24, 2009
Product Specification