DS566 Datasheet, PDF (33/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
Single Data Beat Write Operation
Figure Top x-ref 6
0ns
MPLB_Clk
100ns
200ns
300ns
400ns
M_request
M_abort
M_buslock
M_priority[0:1]
M_ABus[0:31]
M_RNW
M_BE[0:7]
M_MSize[0:1]
M_size[0:3]
M_type[0:2]
M_wrDBus[0:63]
M_wrBurst
M_rdBurst
1
10000002
30
01
0
0
WD0
PLB_MaddrAck
PLB_MSsize[0:1]
01
PLB_MRearbitrate
PLB_MBusy
PLB_MRdrErr
PLB_MWrErr
PLB_MrdBterm
PLB_MrdDAck
PLB_MrdDbus[0:63]
PLB_MwrBterm
PLB_MWrDAck
IP2Bus_MstWr_Req
IP2Bus_MstWr_Addr[0:31]
IP2Bus_MstWr_Length[0:11]
IP2Bus_MstWr_BE[0:7]
IP2Bus_MstWr_Size[0:1]
IP2Bus_MstWr_Type
IP2Bus_MstWr_Lock
IP2Bus_MstWr_Reset
10000002
002
30
X
Bus2IP_MstWr_CmdAck
Bus2IP_MstWr_Cmplt
Bus2IP_MstWr_Error
Bus2IP_MstWr_Rearbitrate
Bus2IP_MstWr_Timeout
Bus2IP_MstWr_Length_is_Zero
IP2Bus_MstWr_clk
IP2Bus_MstWr_src_rdy_n
IP2Bus_MstWr_src_dsc_n
IP2Bus_MstWr_sof_n
IP2Bus_MstWr_sop_n
IP2Bus_MstWr_eop_n
IP2Bus_MstWr_eof_n
IP2Bus_MstWr_d[0:63]
WD0
IP2Bus_MstWr_rem[0:2]
30
Bus2IP_MstWr_dst_rdy_n
Bus2IP_MstWr_dst_dsc_n
Bus2IP_MstWr_WrCnt[0:8]
000
001
DS566_06_033009
Figure 6: PLBV46 Master Single Data Beat Write Timing
DS566 April 24, 2009
www.xilinx.com
33
Product Specification