DS566 Datasheet, PDF (26/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
depending on rem parameterization). Synchronous and asynchronous FIFOs are limited to a maximum
depth of 16K entries.
1. For asynchronous Write FIFOs, this value must be set to a value that is equal to 2ⁿ-1 where n is an integer
value.
2. For synchronous Write FIFOs, this value must be set to a value that is equal to 2ⁿ where n is an integer value.
3. For SRL FIFOs, only values of 16, 32, and 64 are allowed. A depth of 32 or greater is recommended.
C_WRFIFO_WRCNT_WIDTH
This integer parameter applies to the Write Controller. This integer parameter specifies the size of the
Bus2IP_MstWr_WrCnt bus which is internally sourced from the WrFIFO write count output bus and
output to the IP Client as a sideband signal bus with Write LocalLink interface. The value has a range
of 1 to log2(C_WRFIFO_DEPTH)+1. The Bus2IP_MstWr_WrCnt bus is populated from the most
significant bit towards the least significant bit.
Notes:
1. For asynchronous Write FIFOs, this value is set to log₂(C_WRFIFO_DEPTH).
2. For synchronous Write FIFOs (Core Generatpr tool and SRL), this value is set to log₂(C_WRFIFO_DEPTH)+1.
C_WRFIFO_OCCUPANCY_WIDTH
This parameter is reserved and should be set to 1.
C_RD_LLINK_IS_ASYNC
This integer parameter applies to the Write Controllers. This integer parameter specifies the needed
clocking relationship of the Read LocalLink interface and the PLB Bus clock. When set to 1, the Read
LocalLink Interface must be supplied with a User clock and an Asynchronous Core Generator system
FIFO will be instantiated for the Read FIFO. If set to 0, the Read LocalLink Interface will use the PLB
Bus clock and a Synchronous Core Generator system FIFO will be instantiated for the Read FIFO. Note
that asynchronous operation induces more latency in initiating and completing read transfers.
C_USE_SRL_RDFIFO
If the LocalLink interface is synchronous to the PLB Clock as specified by the
C_RD_LLINK_IS_ASYNC, then this parameter allows the User to select the use of an SRL16 based
implementation of the Write FIFO. This will eliminate the use of BRAMs for the FIFO. If selected, the
C_RDFIFO_DEPTH can be 16, 32, or 64.
C_RDFIFO_DEPTH
This parameter specifies the storage depth of the RdFIFO in the Read Controller. The width of the
RdFIFO is automatically set to the value of C_MPLB_NATIVE_DWIDTH plus LocalLink packet
delimiters (2) and LocalLink rem (0 to 16 bits depending on rem parameterization). Synchronous and
asynchronous FIFOs are limited to a maximum depth of 16K entries.
Notes:
1. For asynchronous Read FIFOs, this value must be set to a value that is equal to 2ⁿ-1 where n is an integer
value.
2. For synchronous Read FIFOs, this value must be set to a value that is equal to 2ⁿ where n is an integer value.
3. For SRL FIFOs, only values of 16, 32, and 64 are allowed. It is recommended that a depth of 32 and greater is
used.
C_RDFIFO_RDCNT_WIDTH
This integer parameter applies to the Read LocalLink Backend. It specifies the size of the
Bus2IP_MstRd_RdCnt bus which is internally sourced from the RdFIFO read count bus. The value has
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DS566 April 24, 2009
Product Specification