DS566 Datasheet, PDF (37/38 Pages) Xilinx, Inc – PLBV46 Master

PLBV46 Master (v1.00a)
Table 6: Parameter Settings for Resource Utilization Estimates (Contd)
Parameter Name
Full-up 128-bit Typical 64-bit
C_WR_LLINK_IS_ASYNC
C_USE_SRL_WRFIFO
C_WRFIFO_DEPTH
C_WRFIFO_WRCNT_WIDTH
C_WRFIFO_OCCUPANCY_WIDTH
C_RD_LLINK_IS_ASYNC
C_USE_SRL_RDFIFO
C_RDFIFO_DEPTH
C_RDFIFO_RDCNT_WIDTH
C_RDFIFO_VACANCY_WIDTH
C_RDFIFO_LLTRANS_THRES
C_REM_WIDTH
C_REM_CODING
C_REM_POLARITY
C_MPLB_AWIDTH
C_MPLB_DWIDTH
C_MPLB_NATIVE_DWIDTH
C_MPLB_SMALLEST_SLAVE
C_INHIBIT_CC_BLE_INCLUSION
C_FAMILY
1
0
16383
14
1
1
0
16383
14
1
16
16
2
1
32
128
128
32
0
"virtex5"
0
0
512
10
1
0
0
512
10
1
8
8
2
32
32
64
64
32
0
"virtex5"
32-bit SRL
FIFO
0
1
32
6
1
0
1
32
6
1
4
4
2
32
32
32
32
32
0
"virtex5"
Specification Exceptions
The following PLB Master features are not supported by the PLBV46 Master design.
• Parity
• Indeterminate Length Bursts
• Fixed Length Bursts of length 17 to 256 data beats
• Cacheline transfers
• Bus Locking
The following LocalLink features are not supported:
• Channelization
• Start of payload and End of Payload assertions
• Parity
• Multiple REM bus per LocalLink
DS566 April 24, 2009
www.xilinx.com
37
Product Specification