DS566 Datasheet, PDF(28/38 Page) Xilinx, Inc

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DS566 Datasheet, PDF (28/38 Pages) Xilinx, Inc – PLBV46 Master

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PLBV46 Master (v1.00a)

C_REM_POLARITY

This integer parameter specifies the assertion polarity of the values placed on the Bus2IP_MstRd_rem

and the interpretation of the IP2Bus_MstWr_rem buses during data transmission. Assignment of 0

selects active low assertion and an assignment of 1 selects active high assertion level.

C_MPLB_AWIDTH

This integer parameter is used to specify the number of address bits that are used in the PLB system.

PLB V4.6 has 64 address bits defined. The only allowed value to be assigned is currently restricted to 32.

C_MPLB_DWIDTH

This integer parameter is used to indicate the width of the PLB data bus to which the Master will be

attaching. This value may be set to 32, 64, and 128 but cannot be less than then the value assigned to

C_MPLB_NATIVE_DWIDTH.

C_MPLB_NATIVE_DWIDTH

This integer parameter is used to size the internal data bus related components within the Master as

well as the data width of the LocalLink data interface. The assigned value may be 32, 64, and 128 but

cannot exceed the value assigned to C_MPLB_DWIDTH.

C_MPLB_SMALLEST_SLAVE

This integer parameter indicates the Native Bit Width of the smallest PLB Slave that the Master will

encounter during read and write operations. This parameter is used to optimize write data bus steering

logic and the automatic inclusion of Conversion Cycle and Burst Length Expansion functionality.

Automatic CC and BLE functionality is included if the value for this parameter is less than the value

assigned to C_MPLB_NATIVE_DWIDTH. The assigned value may be 32, 64, and 128 but cannot

exceed the value assigned to C_MPLB_DWIDTH.

C_INHIBIT_CC_BLE_INCLUSION

This parameter allows the User to override the automatic inclusion of Conversion Cycle and Burst

Length Expansion logic. an assigned value of 1 inhibits the CC and BLE inclusion, a 0 is default and

allows for automatic inclusion if needed.

C_FAMILY

This parameter is defined as a string. It identifies the target FPGA technology for implementation of the

PLB46 Master. This parameter is required by the LocalLink FIFO designs which utilize Xilinx BRAM

primitives. The size and configuration of these primitives can vary from one FPGA technology family

to another.

Table 3: Xilinx Predefined Identifiers for FPGA Families

PLB Master